Datasheet > M48Z35AYSH

M48Z35AYSH

更新时间： 2024-11-12 22:06:03

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		静态存储器
页数	文件大小	规格书
16页	127K
描述
256 Kbit 32Kb x8 ZEROPOWER SRAM

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中文翻译

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数据手册

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M48Z35AYSH 数据手册

M48Z35AY

M48Z35AV

256 Kbit (32Kb x8) ZEROPOWER SRAM

■ INTEGRATED ULTRA LOW POWER SRAM,

SNAPHAT (SH)

Battery

POWER-FAIL CONTROL CIRCUIT and

BATTERY

■ READ CYCLE TIME EQUALS WRITE CYCLE

TIME

■ BATTERY LOW FLAG (BOK)

■ AUTOMATIC POWER-FAIL CHIP DESELECT

and WRITE PROTECTION

■ WRITE PROTECT VOLTAGES

PCDIP28 (PC)

Battery CAPHAT

= Power-fail Deselect Voltage):

PFD

– M48Z35AY: 4.20V ≤ V

≤ 4.50V

PFD

SOH28 (MH)

– M48Z35AV: 2.7V ≤ V

≤ 3.0V

PFD

■ SELF-CONTAINED BATTERY in the CAPHAT

DIP PACKAGE

Figure 1. Logic Diagram

■ PACKAGING INCLUDES a 28-LEAD SOIC and

SNAPHAT TOP

(to be Ordered Separately)

■ SOIC PACKAGE PROVIDES DIRECT

CONNECTION for a SNAPHAT TOP which

CONTAINS the BATTERY and CRYSTAL

■ PIN and FUNCTION COMPATIBLE with

JEDEC STANDARD 32K x8 SRAMs

DESCRIPTION

The M48Z35AY/35AV ZEROPOWER RAM is a

A0-A14

DQ0-DQ7

32 Kbit x8 non-volatile static RAM that integrates

power-fail deselect circuitry and battery control

logic on a single die. The monolithic chip is avail-

able in two special packages to provide a highly in-

tegrated battery backed-up memory solution.

M48Z35AY

M48Z35AV

Table 1. Signal Names

A0-A14

Address Inputs

Data Inputs / Outputs

Chip Enable

DQ0-DQ7

AI02781B

Output Enable

Write Enable

Supply Voltage

Ground

April 2000

1/16

12 3 4 5 6 7...16

中文翻译

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