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M48Z35Y-70PC6 PDF预览

M48Z35Y-70PC6

更新时间: 2024-11-12 22:13:35
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 静态存储器
页数 文件大小 规格书
18页 137K
描述
256 Kbit 32Kb x8 ZEROPOWER SRAM

M48Z35Y-70PC6 数据手册

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M48Z35  
M48Z35Y  
®
256 Kbit (32Kb x8) ZEROPOWER SRAM  
INTEGRATED ULTRA LOW POWER SRAM,  
SNAPHAT (SH)  
Battery  
POWER-FAIL CONTROL CIRCUIT and  
BATTERY  
READ CYCLE TIME EQUALS WRITE CYCLE  
TIME  
AUTOMATIC POWER-FAIL CHIP DESELECT  
and WRITE PROTECTION  
28  
WRITE PROTECT VOLTAGES  
(V  
PFD  
= Power-fail Deselect Voltage):  
1
28  
– M48Z35: 4.50V V  
4.75V  
PCDIP28 (PC)  
PFD  
1
Battery CAPHAT  
– M48Z35Y: 4.20V V  
4.50V  
PFD  
SOH28 (MH)  
SELF-CONTAINED BATTERY in the CAPHAT  
DIP PACKAGE  
PACKAGING INCLUDES a 28-LEAD SOIC and  
®
SNAPHAT TOP (to be Ordered Separately)  
Figure 1. Logic Diagram  
SOIC PACKAGE PROVIDES DIRECT  
CONNECTION for a SNAPHAT TOP which  
CONTAINS the BATTERY and CRYSTAL  
PIN and FUNCTION COMPATIBLE with  
JEDEC STANDARD 32K x8 SRAMs  
V
CC  
DESCRIPTION  
The M48Z35/35Y ZEROPOWER RAM is a 32  
Kbit x8 non-volatile static RAM that integrates  
power-fail deselect circuitry and battery control  
logic on a single die. The monolithic chip is avail-  
able in two special packages to provide a highly in-  
tegrated battery backed-up memory solution.  
®
15  
8
A0-A14  
DQ0-DQ7  
W
E
M48Z35  
M48Z35Y  
Table 1. Signal Names  
G
A0-A14  
Address Inputs  
Data Inputs / Outputs  
Chip Enable  
DQ0-DQ7  
E
V
SS  
AI01616D  
G
W
Output Enable  
Write Enable  
Supply Voltage  
Ground  
V
CC  
V
SS  
August 1999  
1/18  

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