M48Z512AV-70PM6

更新时间： 2024-11-13 11:29:31

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		静态存储器
页数	文件大小	规格书
21页	338K
描述
4 Mbit (512 Kbit x 8) ZEROPOWER? SRAM

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中文翻译

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数据手册

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M48Z512AV-70PM6 数据手册

M48Z512A

M48Z512AY, M48Z512AV

4 Mbit (512 Kbit x 8) ZEROPOWER^®SRAM

Features

■ Integrated, ultra low power SRAM, power-fail

control circuit, and battery

■ Conventional SRAM operation; unlimited

WRITE cycles

■ 10 years of data retention in the absence of

power

■ Automatic power-fail chip deselect and WRITE

PMDIP32 module (PM)

protection

■ Two WRITE protect voltages:

= power-fail deselect voltage)

PFD

Description

– M48Z512A:

= 4.75 to 5.5 V, 4.5 V ≤ V

– M48Z512AY:

= 4.5 to 5.5 V, 4.2 V ≤ V

– M48Z512AV:

= 3.0 to 3.6 V, 2.8 V ≤ V

≤ 4.75 V

PFD

The M48Z512A/Y/V ZEROPOWER RAM is a

non-volatile, 4,194,304-bit static RAM organized

as 524,288 words by 8 bits. The devices combine

an internal lithium battery, a CMOS SRAM and a

control circuit in a plastic, 32-pin DIP Module.

≤ 4.5 V

≤ 3.0 V

PFD

M48Z512AV not for new design (see

M48Z512BV). Contact ST sales office for

availability.

■ Battery internally isolated until power is applied

■ Pin and function compatible with JEDEC

standard 512 K x 8 SRAMs

■ PMDIP32 is an ECOPACK package

■ RoHS compliant

– Lead-free second level interconnect

August 2010

Doc ID 5146 Rev 8

1/21

www.st.com

12 3 4 5 6 7...21

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