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M48Z35-70PC1E PDF预览

M48Z35-70PC1E

更新时间: 2024-09-25 03:10:07
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 存储内存集成电路静态存储器
页数 文件大小 规格书
23页 219K
描述
256Kbit (32Kbit x 8) ZEROPOWER SRAM

M48Z35-70PC1E 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:ActiveReach Compliance Code:compliant
HTS代码:8542.32.00.71风险等级:5.69
Is Samacsys:NJESD-609代码:e3
内存集成电路类型:MEMORY CIRCUIT峰值回流温度(摄氏度):NOT SPECIFIED
端子面层:Matte Tin (Sn)处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

M48Z35-70PC1E 数据手册

 浏览型号M48Z35-70PC1E的Datasheet PDF文件第2页浏览型号M48Z35-70PC1E的Datasheet PDF文件第3页浏览型号M48Z35-70PC1E的Datasheet PDF文件第4页浏览型号M48Z35-70PC1E的Datasheet PDF文件第5页浏览型号M48Z35-70PC1E的Datasheet PDF文件第6页浏览型号M48Z35-70PC1E的Datasheet PDF文件第7页 
M48Z35  
M48Z35Y  
256Kbit (32Kbit x 8) ZEROPOWER® SRAM  
Features  
Integrated, ultra low power SRAM, power-fail  
control circuit, and battery  
READ cycle time equals WRITE cycle time  
28  
Automatic power-fail chip deselect and WRITE  
1
protection  
WRITE protect voltages:  
PCDIP28 (PC)  
(V  
= Power-fail Deselect Voltage)  
Battery CAPHAT  
PFD  
– M48Z35: V = 4.75 to 5.5V  
CC  
4.5V V  
4.75V  
PFD  
– M48Z35Y: 4.5 to 5.5V  
SNAPHAT (SH)  
Battery  
4.2v V 4.5v  
pfd  
Self-contained battery in the CAPHAT™ DIP  
package  
Packaging includes a 28-lead SOIC and  
®
SNAPHAT top (to be ordered separately)  
Pin and function compatible with JEDEC  
standard 32K x 8 SRAMs  
28  
SOIC package provides direct connection for a  
1
SNAPHAT top which contains the battery  
RoHS compliant  
SOH28 (MH)  
Lead-free second level interconnect  
November 2007  
Rev 7  
1/23  
www.st.com  
1

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