Datasheet > M48Z35-70MH6TR

M48Z35-70MH6TR

更新时间： 2024-09-24 22:08:19

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		静态存储器
页数	文件大小	规格书
18页	137K
描述
256 Kbit 32Kb x8 ZEROPOWER SRAM

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中文翻译

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数据手册

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M48Z35-70MH6TR 数据手册

M48Z35

M48Z35Y

256 Kbit (32Kb x8) ZEROPOWER SRAM

■ INTEGRATED ULTRA LOW POWER SRAM,

SNAPHAT (SH)

Battery

POWER-FAIL CONTROL CIRCUIT and

BATTERY

■ READ CYCLE TIME EQUALS WRITE CYCLE

TIME

■ AUTOMATIC POWER-FAIL CHIP DESELECT

and WRITE PROTECTION

■ WRITE PROTECT VOLTAGES

PFD

= Power-fail Deselect Voltage):

– M48Z35: 4.50V ≤ V

≤ 4.75V

PCDIP28 (PC)

PFD

Battery CAPHAT

– M48Z35Y: 4.20V ≤ V

≤ 4.50V

PFD

SOH28 (MH)

■ SELF-CONTAINED BATTERY in the CAPHAT

DIP PACKAGE

■ PACKAGING INCLUDES a 28-LEAD SOIC and

SNAPHAT TOP (to be Ordered Separately)

Figure 1. Logic Diagram

■ SOIC PACKAGE PROVIDES DIRECT

CONNECTION for a SNAPHAT TOP which

CONTAINS the BATTERY and CRYSTAL

■ PIN and FUNCTION COMPATIBLE with

JEDEC STANDARD 32K x8 SRAMs

DESCRIPTION

The M48Z35/35Y ZEROPOWER RAM is a 32

Kbit x8 non-volatile static RAM that integrates

power-fail deselect circuitry and battery control

logic on a single die. The monolithic chip is avail-

able in two special packages to provide a highly in-

tegrated battery backed-up memory solution.

A0-A14

DQ0-DQ7

M48Z35

M48Z35Y

Table 1. Signal Names

A0-A14

Address Inputs

Data Inputs / Outputs

Chip Enable

DQ0-DQ7

AI01616D

Output Enable

Write Enable

Supply Voltage

Ground

August 1999

1/18

12 3 4 5 6 7...18

中文翻译

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