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M30W0R6500T0ZAQT PDF预览

M30W0R6500T0ZAQT

更新时间: 2024-10-29 19:46:19
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 可编程只读存储器内存集成电路
页数 文件大小 规格书
19页 112K
描述
6MX16 FLASH 3.3V PROM MODULE, PBGA88, 8 X 10 MM, 0.80 MM PITCH, TFBGA-88

M30W0R6500T0ZAQT 技术参数

生命周期:Transferred零件包装代码:BGA
包装说明:8 X 10 MM, 0.80 MM PITCH, TFBGA-88针数:88
Reach Compliance Code:unknownECCN代码:3A991.B.1.A
HTS代码:8542.32.00.51风险等级:5.56
其他特性:SYNCHRONOUS BURST MODE OPERATION POSSIBLE启动块:TOP
JESD-30 代码:R-PBGA-B88长度:10 mm
内存密度:100663296 bit内存集成电路类型:FLASH MODULE
内存宽度:16功能数量:1
端子数量:88字数:6291456 words
字数代码:6000000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:6MX16封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
编程电压:3.3 V认证状态:Not Qualified
座面最大高度:1.4 mm最大供电电压 (Vsup):2.2 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
类型:NOR TYPE宽度:8 mm
Base Number Matches:1

M30W0R6500T0ZAQT 数据手册

 浏览型号M30W0R6500T0ZAQT的Datasheet PDF文件第2页浏览型号M30W0R6500T0ZAQT的Datasheet PDF文件第3页浏览型号M30W0R6500T0ZAQT的Datasheet PDF文件第4页浏览型号M30W0R6500T0ZAQT的Datasheet PDF文件第5页浏览型号M30W0R6500T0ZAQT的Datasheet PDF文件第6页浏览型号M30W0R6500T0ZAQT的Datasheet PDF文件第7页 
M30W0R6500T0  
96 Mbit (64 + 32Mb, x16, Multiple Bank, Burst, Flash Memories)  
1.8V Supply, Multi-Chip Package  
FEATURES SUMMARY  
MULTI-CHIP PACKAGE  
Figure 1. Packages  
1 die of 64 Mbit (4Mb x 16) Flash Memory  
1 die of 32 Mbit (2Mb x 16) Flash Memory  
SUPPLY VOLTAGE  
VDDF1 = VDDF2 = VDDQ = 1.7 to 2.2V  
VPP = 12V for fast Program (optional)  
LOW POWER CONSUMPTION  
ELECTRONIC SIGNATURE  
FBGA  
Manufacturer Code: 20h  
64Mb Device Code (Top Configuration):  
8810h  
32Mb Device Code (Top Configuration):  
8814h  
Stacked LFBGA88 (ZA)  
8 x 10mm  
PACKAGE  
Compliant with Lead-Free Soldering  
Processes  
Lead-Free Versions  
FLASH MEMORY  
BLOCK LOCKING  
SYNCHRONOUS / ASYNCHRONOUS READ  
All blocks locked at Power up  
Any combination of blocks can be locked  
WP for Block Lock-Down  
Synchronous Burst Read mode: 54MHz  
Asynchronous/ Synchronous Page Read  
mode  
SECURITY  
Random Access: 70ns  
128 bit user programmable OTP cells  
64 bit unique device number  
One parameter block permanently  
lockable  
PROGRAMMING TIME  
8µs by Word typical for Fast Factory  
Program  
Double/Quadruple Word Program option  
Enhanced Factory Program options  
COMMON FLASH INTERFACE (CFI)  
100,000 PROGRAM/ERASE CYCLES per  
BLOCK  
ARCHITECTURE  
64Mbit and 32Mbit Flash memories  
Multiple Bank Memory Array: 4 Mbit  
Banks  
Parameter Blocks (Top location)  
DUAL OPERATIONS  
Program Erase in one Bank while Read in  
others  
No delay between Read and Write  
operations  
December 2004  
1/19  
 
 
 

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