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M30XXLFXI PDF预览

M30XXLFXI

更新时间: 2024-10-29 15:44:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟外围集成电路晶体
页数 文件大小 规格书
16页 722K
描述
Clock Generator, 50MHz, CMOS, 4 X 4 MM, 1 MM HEIGHT, LEAD FREE, MO-220, QFN-24

M30XXLFXI 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:QFN包装说明:HVQCCN,
针数:24Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.24其他特性:CUSTOMER SPECIFIC FREQUENCY CONFIGURATION
JESD-30 代码:S-XQCC-N24JESD-609代码:e3
长度:4 mm湿度敏感等级:3
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:50 MHz
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260主时钟/晶体标称频率:48 MHz
认证状态:Not Qualified座面最大高度:1 mm
最大供电电压:1.95 V最小供电电压:1.65 V
标称供电电压:1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:4 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

M30XXLFXI 数据手册

 浏览型号M30XXLFXI的Datasheet PDF文件第2页浏览型号M30XXLFXI的Datasheet PDF文件第3页浏览型号M30XXLFXI的Datasheet PDF文件第4页浏览型号M30XXLFXI的Datasheet PDF文件第5页浏览型号M30XXLFXI的Datasheet PDF文件第6页浏览型号M30XXLFXI的Datasheet PDF文件第7页 
MoBL® Clock  
M3000/M6000  
Three-PLL Programmable Clock Generator  
for Portable Applications  
Features  
Benefits  
Device operating voltage options:  
MoBL® Clock M3000 family: 1.8 V  
Suitable for cell phone, portable, and consumer electronics  
applications  
MoBL Clock M6000 family: 2.5 V, 3.0 V, or 3.3 V  
Replaces multiple crystals or crystal oscillators saving board  
space  
Selectable clock output voltages for both MoBL clock M3000  
and M6000:  
1.5 V, 1.8 V, 2.5 V, 3.0 V, or 3.3 V  
Multiple high-performance PLLs allow synthesis of unrelated  
frequencies  
Fully integrated ultra-low power phase-locked loops (PLLs)  
Capable of zero parts per million (PPM) frequency synthesis  
error  
Input reference clock frequency range:  
External crystal: 8 to 48 MHz  
Application compatibility in multiple output voltage levels  
External reference: 1- to 48-MHz clock  
Optional Spread Spectrum capable-PLLs with Lexmark or  
Linear profile for maximum electromagnetic interference (EMI)  
reduction  
Output clock frequency range: 3 to 50 MHz  
Up to eight I2C programmable output clocks  
Programmable output drive strengths  
150 ps typical cycle-to-cycle jitter  
Programmable PLLs for system frequency margin tests  
Meets critical timing requirements in complex system designs  
Individually enable or disable each output using I2C  
Optional Spread Spectrum for EMI reduction  
24-pin (4 × 4 × 1 mm) quad flat no leads (QFN) package  
Industrial temperature range  
Ease of output clock selection using programmable crossbar  
switches  
Logic Block Diagram  
CLK1  
XIN/  
EXCLKIN  
Bank  
1
CLK2  
Crossbar  
Switch  
Output  
Dividers  
and  
OSC  
PLL1  
XOUT  
CLK3  
CLK4  
CLK5  
CLK6  
CLK7  
CLK8  
Drive  
Bank  
2
Strength  
Control  
PLL2  
(SS)  
MUX  
and  
Control  
Logic  
Bank  
3
PLL3  
(SS)  
SCL  
SDA  
I2C  
SSON  
PD #/ OE  
Cypress Semiconductor Corporation  
Document #: 001-29159 Rev. *C  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised August 17, 2010  
[+] Feedback  

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