Datasheet > M29F002NT-70P1

M29F002NT-70P1

更新时间： 2024-02-06 15:53:25

品牌	Logo	应用领域
恒忆 - NUMONYX		可编程只读存储器光电二极管内存集成电路
页数	文件大小	规格书
29页	233K
描述
256KX8 FLASH 5V PROM, 70ns, PDIP32, 0.600 INCH, PLASTIC, DIP-32

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M29F002NT-70P1 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
零件包装代码：	DIP	包装说明：	DIP, DIP32,.6
针数：	32	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.32.00.51
风险等级：	5.28	最长访问时间：	70 ns
其他特性：	20 YEARS DATA RETENTION; 100000 PROGRAM/ERASE CYCLES; TOP BOOT BLOCK	启动块：	TOP
命令用户界面：	YES	数据轮询：	YES
数据保留时间-最小值：	20	耐久性：	100000 Write/Erase Cycles
JESD-30 代码：	R-PDIP-T32	JESD-609代码：	e0
长度：	41.91 mm	内存密度：	2097152 bit
内存集成电路类型：	FLASH	内存宽度：	8
功能数量：	1	部门数/规模：	1,2,1,3
端子数量：	32	字数：	262144 words
字数代码：	256000	工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256KX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装等效代码：	DIP32,.6
封装形状：	RECTANGULAR	封装形式：	IN-LINE
并行/串行：	PARALLEL	电源：	5 V
编程电压：	5 V	认证状态：	Not Qualified
座面最大高度：	5.08 mm	部门规模：	16K,8K,32K,64K
最大待机电流：	0.0001 A	子类别：	Flash Memories
最大压摆率：	0.02 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	切换位：	YES
类型：	NOR TYPE	宽度：	15.24 mm
Base Number Matches：	1

M29F002NT-70P1 数据手册

M29F002T, M29F002NT, M29F002B

Table 8. Instructions ⁽¹⁾

Mne.

Instr.

Cyc.

1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc.

Addr. ^(3,7)

Data

Read Memory Array until a new write cycle is initiated.

Read/Reset

Memory Array

RD ^(2,4)

F0h

Addr. ^(3,7)

555h

AAh

AAAh

55h

555h

F0h

Read Memory Array until a new write

cycle is initiated.

Data

Addr. ^(3,7)

555h

AAAh

555h

Read Electronic Signature or Block

Protection Status until a new write cycle

is initiated. See Note 5 and 6.

AS ⁽⁴⁾Auto Select

Data

AAh

55h

90h

Program

Address

Addr. ^(3,7)

555h

AAAh

555h

Read Data Polling or Toggle

Bit until Program completes.

Program

Data

AAh

55h

A0h

Block

Additional

Addr. ^(3,7)

555h

AAAh

555h

AAAh

Address Block ⁽⁸⁾

Block Erase

Chip Erase

Data

AAh

555h

AAh

55h

AAAh

55h

80h

555h

80h

AAh

555h

AAh

55h

AAAh

55h

30h

555h

10h

30h

Addr. ^(3,7)

ES ⁽¹⁰⁾

Note 9

Data

Addr. ^(3,7)

Data

Erase

Suspend

Read until Toggle stops, then read all the data needed from

any Block(s) not being erased then Resume Erase.

B0h

Addr. ^(3,7)

Erase

Resume

Read Data Polling or Toggle Bits until Erase completes or

Erase is suspended another time

Data

30h

Notes: 1. Commands not interpreted in this table will default to read array mode.

2. A wait of t_PLYHis necessary after a Read/Reset command if the memory was in an Erase or Program mode

before starting any new operation (see Table 14 and Figure 9).

3. X = Don’t Care.

4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after

the command cycles.

5. Signature Address bits A0, A1 at V_ILwill output Manufacturer code (20h). Address bits A0 at V_IHand A1 at V_ILwill output

Device code.

6. Block Protection Address: A0 at V_IL, A1 at V_IHand A13-A17 within the Block will output the Block Protection status.

7. For Coded cycles address inputs A12-A17 are don’t care.

8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry,

timeout status can be verified through DQ3 value (see Erase Timer Bit DQ3 description).

When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended.

9. Read Data Polling, Toggle bits or RB until Erase completes.

10.During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.

The instructions require from 1 to 6 cycles, the first

or first three of which are always write operations

used to initiate the instruction.They are followed by

either further write cycles to confirm the first com-

mand or execute the command immediately. Com-

mand sequencing must be followed exactly. Any

invalid combination of commands will reset the

device to Read Array. The increased number of

cycles has been chosen to assure maximum data

security. Instructions are initialised by two initial

Coded cycles which unlock the Command Inter-

face. In addition, for Erase, instruction confirmation

is again preceded by the two Coded cycles.

Status Register Bits

P/E.C. status is indicated during execution by Data

Polling on DQ7, detection of Toggle on DQ6 and

DQ2, or Error on DQ5 and Erase Timer DQ3 bits.

Any read attempt during Program or Erase com-

mand execution will automatically output these five

Status Register bits. The P/E.C. automatically sets

bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits

(DQ0, DQ1 and DQ4) are reserved for future use

and should be masked. See Tables 9 and 10.

8/29

1...5 6 789 10 11...29

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