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M27V402-200F5 PDF预览

M27V402-200F5

更新时间: 2024-10-29 07:00:47
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 可编程只读存储器电动程控只读存储器内存集成电路
页数 文件大小 规格书
15页 181K
描述
256KX16 UVPROM, 200ns, CDIP40, FRIT SEALED, WINDOWED, CERAMIC, DIP-40

M27V402-200F5 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:FRIT SEALED, WINDOWED, CERAMIC, DIP-40
针数:40Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.61
风险等级:5.92最长访问时间:200 ns
I/O 类型:COMMONJESD-30 代码:R-GDIP-T40
JESD-609代码:e0长度:52.195 mm
内存密度:4194304 bit内存集成电路类型:UVPROM
内存宽度:16功能数量:1
端子数量:40字数:262144 words
字数代码:256000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-20 °C
组织:256KX16输出特性:3-STATE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:WDIP
封装等效代码:DIP40,.6封装形状:RECTANGULAR
封装形式:IN-LINE, WINDOW并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified座面最大高度:5.72 mm
最大待机电流:0.00002 A子类别:EPROMs
最大压摆率:0.02 mA最大供电电压 (Vsup):3.63 V
最小供电电压 (Vsup):2.97 V标称供电电压 (Vsup):3.3 V
表面贴装:NO技术:CMOS
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:15.24 mm

M27V402-200F5 数据手册

 浏览型号M27V402-200F5的Datasheet PDF文件第2页浏览型号M27V402-200F5的Datasheet PDF文件第3页浏览型号M27V402-200F5的Datasheet PDF文件第4页浏览型号M27V402-200F5的Datasheet PDF文件第5页浏览型号M27V402-200F5的Datasheet PDF文件第6页浏览型号M27V402-200F5的Datasheet PDF文件第7页 
M27V402  
4 Mbit (256Kb x16) Low Voltage UV EPROM and OTP EPROM  
NOT FOR NEW DESIGN  
M27V402 is replaced by the M27W402  
LOW VOLTAGE READ OPERATION:  
3V to 3.6V  
ACCESS TIME: 120ns  
LOW POWER CONSUMPTION:  
40  
40  
– Active Current 15mA at 5MHz  
1
1
– Standby Current 20µA  
FDIP40W (F)  
PDIP40 (B)  
PROGRAMMING VOLTAGE: 12.75V ± 0.25V  
PROGRAMMING TIME: 100µs/word  
ELECTRONIC SIGNATURE  
– Manufacturer Code: 20h  
– Device Code: 8Dh  
DESCRIPTION  
PLCC44 K)  
TSOP40 (N)  
10 x 20 mm  
The M27V402 is a low voltage, low power 4 Mbit  
UV erasable and electrically programmable  
EPROM, ideally suited for handheld and portable  
microprocessor systems requiring large programs.  
It is organized as 262,144 by 16 bits.  
Figure 1. Logic Diagram  
The M27V402 operates in the read mode with a  
supply voltage as low as 3V. The decrease in op-  
erating power allows either a reduction of the size  
of the battery or an increase in the time between  
battery recharges.  
V
V
PP  
CC  
The FDIP40W (window ceramc frit-seal package)  
has a transparent lid which alws the user to ex-  
pose the chip to ultraviolet light to erase the bit pat-  
tern. A new pattern can then be written to the  
device by following the programming procedure.  
18  
16  
A0-A17  
Q0-Q15  
For applications where the content is programmed  
only one time and erasure is not required, the  
M27V2is offered in PDIP40, PLCC44 and  
TSOP40 (10 x 20 mm) packages.  
E
M27V402  
G
V
SS  
AI01819  
July 2000  
1/15  
This is information on a product still in production but not recommended for new designs.  

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