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M1A3PE3000-FGG484YC PDF预览

M1A3PE3000-FGG484YC

更新时间： 2024-09-21 15:38:43
品牌 Logo 应用领域
美高森美 - MICROSEMI 时钟栅可编程逻辑
页数 文件大小 规格书
162页 8219K
描述
FPGA

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M1A3PE3000-FGG484YC 技术参数

生命周期：Active包装说明：BGA, BGA484,22X22,40
Reach Compliance Code：unknown风险等级：5.74
最大时钟频率：350 MHzJESD-30 代码：S-PBGA-B484
JESD-609代码：e1湿度敏感等级：3
输入次数：341逻辑单元数量：75264
输出次数：341端子数量：484
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA484,22X22,40封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：250
电源：1.5/3.3 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified子类别：Field Programmable Gate Arrays
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
Base Number Matches：1

M1A3PE3000-FGG484YC 数据手册

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Revision 10  
ProASIC3E Flash Family FPGAs  
with Optional Soft ARM Support  
Features and Benefits  
Pro (Professional) I/O  
•
•
•
•
700 Mbps DDR, LVDS-Capable I/Os  
High Capacity  
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation  
Bank-Selectable I/O Voltages—up to 8 Banks per Chip  
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /  
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS  
2.5 V / 5.0 V Input  
•
•
•
600 k to 3 Million System Gates  
108 to 504 kbits of True Dual-Port SRAM  
Up to 620 User I/Os  
Reprogrammable Flash Technology  
•
•
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and  
M-LVDS  
Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL  
2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3  
Class I and II  
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS  
Process  
•
•
•
Live at Power-Up (LAPU) Level 0 Support  
Single-Chip Solution  
Retains Programmed Design when Powered Off  
•
•
•
•
•
•
•
•
I/O Registers on Input, Output, and Enable Paths  
Hot-Swappable and Cold Sparing I/Os  
Programmable Output Slew Rate and Drive Strength  
Programmable Input Delay  
Schmitt Trigger Option on Single-Ended Inputs  
Weak Pull-Up/-Down  
On-Chip User Nonvolatile Memory  
•
1 kbit of FlashROM with Synchronous Interfacing  
High Performance  
•
•
350 MHz System Performance  
3.3 V, 66 MHz 64-Bit PCI  
IEEE 1149.1 (JTAG) Boundary Scan Test  
Pin-Compatible Packages across the ProASIC 3E Family  
In-System Programming (ISP) and Security  
®
•
ISP Using On-Chip 128-Bit Advanced Encryption Standard  
(AES) Decryption via JTAG (IEEE 1532–compliant)  
Clock Conditioning Circuit (CCC) and PLL  
®
•
FlashLock Designed to Secure FPGA Contents  
•
•
Six CCC Blocks, Each with an Integrated PLL  
Configurable Phase-Shift, Multiply/Divide, Delay Capabilities  
and External Feedback  
Low Power  
•
•
•
Core Voltage for Low Power  
Support for 1.5-V-Only Systems  
Low-Impedance Flash Switches  
•
Wide Input Frequency Range (1.5 MHz to 200 MHz)  
SRAMs and FIFOs  
•
Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,  
and ×18 organizations available)  
High-Performance Routing Hierarchy  
•
•
•
•
•
Segmented, Hierarchical Routing and Clock Structure  
Ultra-Fast Local and Long-Line Network  
Enhanced High-Speed, Very-Long-Line Network  
High-Performance, Low-Skew Global Network  
Architecture Supports Ultra-High Utilization  
•
•
True Dual-Port SRAM (except ×18)  
24 SRAM and FIFO Configurations with Synchronous Operation  
up to 350 MHz  
ARM® Processor Support in ProASIC3E FPGAs  
•
M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available  
with or without Debug  
Table 1-1 • ProASIC3E Product Family  
ProASIC3E Devices  
A3PE600  
A3PE1500  
A3PE3000  
1
Cortex-M1 Devices  
M1A3PE1500  
M1A3PE3000  
System Gates  
600,000  
13,824  
108  
24  
1,500,000  
3,000,000  
VersaTiles (D-flip-flops)  
RAM Kbits (1,024 bits)  
4,608-Bit Blocks  
38,400  
270  
60  
75,264  
504  
112  
1
FlashROM Kbits  
1
1
Secure (AES) ISP  
Yes  
6
Yes  
6
Yes  
6
2
CCCs with Integrated PLLs  
3
VersaNet Globals  
18  
18  
18  
I/O Banks  
8
8
8
Maximum User I/Os  
270  
444  
620  
Package Pins  
PQFP  
FBGA  
PQ208  
FG256, FG484  
PQ208  
FG484, FG676  
PQ208  
FG324, FG484, FG896  
Notes:  
1. Refer to the Cortex-M1 product brief for more information.  
2. The PQ208 package supports six CCCs and two PLLs.  
3. Six chip (main) and three quadrant global networks are available.  
4. For devices supporting lower densities, refer to the ProASIC3 Flash Family FPGAs datasheet.  
March 2012  
I
© 2012 Microsemi Corporation  
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与M1A3PE3000-FGG484YC相关器件

型号 品牌 获取价格 描述 数据表
M1A3PE3000-FGG484YI MICROSEMI

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 		Field Programmable Gate Array, 350MHz, 75264-Cell, CMOS, PBGA484
M1A3PE3000-FGG896 ACTEL

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 		ProASIC3E Flash Family FPGAs
M1A3PE3000-FGG896ES ACTEL

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 		ProASIC3E Flash Family FPGAs
M1A3PE3000-FGG896I ACTEL

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 		ProASIC3E Flash Family FPGAs
M1A3PE3000-FGG896I MICROSEMI

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 		Field Programmable Gate Array, 75264 CLBs, 3000000 Gates, 350MHz, 75264-Cell, CMOS, PBGA89
M1A3PE3000-FGG896PP ACTEL

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 		ProASIC3E Flash Family FPGAs
M1A3PE3000-FGG896Y MICROSEMI

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 		Field Programmable Gate Array, 350MHz, 75264-Cell, CMOS, PBGA896,
M1A3PE3000-FGG896YC MICROSEMI

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 		FPGA
M1A3PE3000-FGG896YI MICROSEMI

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 		FPGA
M1A3PE3000-FPQ208 ACTEL

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 		Field Programmable Gate Array, 75264 CLBs, 3000000 Gates, 350MHz, 75264-Cell, CMOS, PQFP20

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