Datasheet > M1040-13I167.3316

M1040-13I167.3316

更新时间： 2024-09-16 14:52:47

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
12页	430K
描述
PLL/Frequency Synthesis Circuit

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M1040-13I167.3316 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	,	Reach Compliance Code：	unknown
风险等级：	5.92	Base Number Matches：	1

M1040-13I167.3316 数据手册

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P r e l i m i n a r y I n f o r m a t i o n

Integrated

Circuit

Systems, Inc.

M1040

VCSO BASED CLOCK PLL WITH AUTOSWITCH

GENERAL DESCRIPTION

The M1040 is a VCSO (Voltage Controlled SAW

Oscillator) based clock generator

PIN ASSIGNMENT (9 x 9 mm SMT)

PLL designed for clock protection,

frequency translation and jitter

attenuation in OC-12/48 class optical

networking systems. It features dual

differential inputs with two modes of

input selection: manual and

MR_SEL1

MR_SEL0

REF_ACK

LOL

P_SEL

INIT

nFOUT0

FOUT0

GND

nFOUT1

FOUT1

VCC

automatic upon clock failure. The clock multiplication

ratios and output divider ratio are pin selectable. This

device provides two outputs. External loop components

allow the tailoring of PLL loop response.

M1040

NBW

VCC

( T o p V i e w )

DNC

GND

FEATURES

◆ Integrated SAW (surface acoustic wave) delay line;

low phase jitter of < 0.5ps rms, typical (12kHz to

20MHz)

◆ Output frequencies of 62.5 to 175 MHz ^*; Two differen-

tial LVPECL outputs (CML, LVDS options available)

Figure 1: Pin Assignment

Example I/O Clock Frequency Combinations

Using M1040-11-155.5200

◆ Loss of Lock (LOL) indicator output

◆ Narrow Bandwidth control input (NBW pin);

Initialization (INIT) input overrides NBW at power-up

◆ Dual reference clock inputs support LVDS, LVPECL,

PLL Ratio

Output Clock

Input Reference

Clock (MHz)

LVCMOS, LVTTL

(Pin Selectable)

(MHz)

(Pin Selectable)

◆ AutoSwitch (AUTO pin) - automatic (non-revertive)

reference clock reselection upon clock failure; Hitless

Switching (HS), Phase Build-out (PBO) options enable

SONET (GR-253)/SDH (G.813) MTIE/TDEV compliance

19.44

77.76

155.52

622.08

155.52

77.76

◆ Acknowledge pin (REF_ACK pin) indicates the actively

selected reference input

0.25

Table 1: Example I/O Clock Frequency Combinations

* Specify VCSO center frequency at time of order.

◆ Industrial temperature available

◆ Single 3.3V power supply

◆ Small 9 x 9 mm SMT (surface mount) package

SIMPLIFIED BLOCK DIAGRAM

Loop Filter

M1040

NBW

PLL

Phase

MUX

Detector

DIF_REF0

nDIF_REF0

R Div

VCSO

DIF_REF1

nDIF_REF1

REF_ACK

REF_SEL

M Divider

LOL

Phase

AUTO

Detector

Auto

Ref Sel

INIT

LOL

FOUT0

nFOUT0

P Divider

(1 or 2)

M / R Divider

LUT

FOUT1

MR_SEL2:0

nFOUT1

P_SEL

Figure 2: Simplified Block Diagram

M1040 Datasheet Rev 0.1

Revised 11Nov2003

M1040 VCSO Based Clock PLL with AutoSwitch

Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400

12 3 4 5 6 7...12

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