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LTC2222-11 PDF预览

LTC2222-11

更新时间: 2024-11-28 05:43:43
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凌特 - Linear /
页数 文件大小 规格书
24页 578K
描述
11-Bit, 105Msps ADC

LTC2222-11 数据手册

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LTC2222-11  
11-Bit, 105Msps ADC  
U
FEATURES  
DESCRIPTIO  
The LTC®2222-11 is a 105Msps, sampling 11-bit A/D  
converter designed for digitizing high frequency, wide  
dynamic range signals. The LTC2222-11 is perfect for  
demanding communications applications with AC perfor-  
mance that includes 65.4dB SNR and 80dB spurious free  
dynamic range for signals up to 150MHz. Ultralow jitter of  
0.15psRMS allows undersampling of IF frequencies with  
excellent noise performance.  
Sample Rate: 105Msps  
65.4dB SNR up to 140MHz Input  
80dB SFDR up to 150MHz Input  
775MHz Full Power Bandwidth S/H  
Single 3.3V Supply  
Low Power Dissipation: 475mW  
CMOS Outputs  
Selectable Input Ranges: ±0.5V or ±1V  
No Missing Codes  
DC specs include ±0.15LSB INL (typ), ±0.1LSB DNL (typ)  
Optional Clock Duty Cycle Stabilizer  
and no missing codes over temperature. The transition  
Shutdown and Nap Modes  
noise is a low 0.25LSBRMS  
.
Data Ready Output Clock  
A separate output power supply allows the CMOS output  
swing to range from 0.5V to 3.3V.  
Pin Compatible Family  
135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit)  
105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit)  
80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit)  
48-Pin 7mm × 7mm QFN Package  
The ENC+ and ENCinputs may be driven differentially or  
singleendedwithasinewave, PECL, LVDS, TTL, orCMOS  
inputs. An optional clock duty cycle stabilizer allows high  
performance at full speed for a wide range of clock duty  
cycles.  
U
APPLICATIO S  
, LTC and LT are registered trademarks of Linear Technology Corporation.  
All other trademarks are the property of their respective owners.  
Wireless and Wired Broadband Communication  
Cable Head-End Systems  
Power Amplifier Linearization  
Communications Test Equipment  
U
TYPICAL APPLICATIO  
3.3V  
SFDR vs Input Frequency  
V
DD  
95  
REFH  
REFL  
FLEXIBLE  
90  
85  
80  
75  
70  
65  
60  
55  
50  
0.5V TO 3.3V  
OV  
REFERENCE  
4th OR HIGHER  
DD  
D10  
+
11-BIT  
PIPELINED  
ADC CORE  
CORRECTION  
LOGIC  
ANALOG  
INPUT  
OUTPUT  
DRIVERS  
INPUT  
S/H  
2nd OR 3rd  
D0  
OGND  
CLOCK/DUTY  
CYCLE  
CONTROL  
200  
300  
0
100  
400  
500  
600  
222211 TA01  
INPUT FREQUENCY (MHz)  
ENCODE  
INPUT  
222211 TA01b  
222211f  
1

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