Datasheet > LTC2223

LTC2223

更新时间： 2024-11-27 14:57:19

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
28页	923K
描述
12 位、80Msps ADC

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中文翻译

获取价格

数据手册

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LTC2223 数据手册

LTC2222/LTC2223

12-Bit,105Msps/

80Msps ADCs

FEATURES

DESCRIPTION

The LTC^®2222 and LTC2223 are 105Msps/80Msps, sam-

pling 12-bit A/D converters designed for digitizing high

frequency, wide dynamic range signals. The LTC2222/

LTC2223 are perfect for demanding communications

applications with AC performance that includes 68dB

SNR and 80dB spurious free dynamic range for signals

Sample Rate: 105Msps/80Msps

68dB SNR up to 140MHz Input

80dB SFDR up to 170MHz Input

775MHz Full Power Bandwidth S/H

Single 3.3V Supply

Low Power Dissipation: 475mW/366mW

Selectable Input Ranges: 0.5V or 1V

up to 170MHz. Ultralow jitter of 0.15ps

undersampling of IF frequencies with excellent noise

performance.

allows

RMS

No Missing Codes

Optional Clock Duty Cycle Stabilizer

Shutdown and Nap Modes

DC specs include 0.3LSB INL (typ), 0.2LSB DNL (typ)

and no missing codes over temperature. The transition

Data Ready Output Clock

Pin Compatible Family

noise is a low 0.5LSB

RMS

135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit)

105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit)

80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit)

A separate output power supply allows the outputs to

drive 0.5V to 3.6V logic.

48-Pin QFN Package

–

The ENC and ENC inputs may be driven differentially

or single ended with a sine wave, PECL, LVDS, TTL, or

CMOS inputs. An optional clock duty cycle stabilizer al-

lows high performance at full speed for a wide range of

clock duty cycles.

APPLICATIONS

Wireless and Wired Broadband Communication

Cable Head-End Systems

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Power Ampliﬁer Linearization

Communications Test Equipment

TYPICAL APPLICATION

3.3V

SFDR vs Input Frequency

100

REFH

REFL

FLEXIBLE

REFERENCE

4th OR HIGHER

0.5V TO 3.6V

D11

12-BIT

PIPELINED

ADC CORE

•

CORRECTION

LOGIC

ANALOG

INPUT

OUTPUT

DRIVERS

INPUT

S/H

2nd or 3rd

–

0GND

CLOCK/DUTY

CYCLE

CONTROL

100

200

300

400

500

600

INPUT FREQUENCY (MHz)

22223 TA01b

22223 TA01

ENCODE

INPUT

22223fb

12 3 4 5 6 7...28

中文翻译

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