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LTC2224 PDF预览

LTC2224

更新时间: 2024-11-29 14:58:23
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
24页 610K
描述
12 位、135Msps ADC

LTC2224 数据手册

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LTC2224  
12-Bit, 135Msps ADC  
U
FEATURES  
DESCRIPTIO  
The LTC®2224 is a 135Msps, sampling 12-bit A/D con-  
verter designed for digitizing high frequency, wide dy-  
namic range signals. The LTC2224 is perfect for demand-  
ing communications applications with AC performance  
that includes 67.3dB SNR and 80dB spurious free dy-  
namic range for signals up to 150MHz. Ultralow jitter of  
0.15psRMS allows undersampling of IF frequencies with  
excellent noise performance.  
Sample Rate: 135Msps  
67.3dB SNR up to 140MHz Input  
80dB SFDR up to 150MHz Input  
775MHz Full Power Bandwidth S/H  
Single 3.3V Supply  
Low Power Dissipation: 630mW  
CMOS Outputs  
Selectable Input Ranges: ±0.5V or ±1V  
No Missing Codes  
DC specs include ±0.4LSB INL (typ), ±0.3LSB DNL (typ)  
Optional Clock Duty Cycle Stabilizer  
and no missing codes over temperature. The transition  
Shutdown and Nap Modes  
noise is a low 0.5LSBRMS  
.
Data Ready Output Clock  
A separate output power supply allows the CMOS output  
swing to range from 0.5V to 3.6V.  
Pin Compatible Family  
135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit)  
105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit)  
80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit)  
48-Pin 7mm × 7mm QFN Package  
The ENC+ and ENCinputs may be driven differentially or  
singleendedwithasinewave, PECL, LVDS, TTL, orCMOS  
inputs. An optional clock duty cycle stabilizer allows high  
performance at full speed for a wide range of clock duty  
cycles.  
U
APPLICATIO S  
, LTC and LT are registered trademarks of Linear Technology Corporation.  
All other trademarks are the property of their respective owners.  
Wireless and Wired Broadband Communication  
Cable Head-End Systems  
Power Amplifier Linearization  
Communications Test Equipment  
U
TYPICAL APPLICATIO  
3.3V  
SFDR vs Input Frequency  
V
DD  
95  
REFH  
REFL  
FLEXIBLE  
90  
85  
80  
75  
70  
65  
60  
55  
50  
0.5V TO 3.6V  
REFERENCE  
4th OR HIGHER  
OV  
DD  
D11  
+
12-BIT  
PIPELINED  
ADC CORE  
CORRECTION  
LOGIC  
2nd OR 3rd  
ANALOG  
INPUT  
OUTPUT  
DRIVERS  
INPUT  
S/H  
D0  
OGND  
CLOCK/DUTY  
CYCLE  
CONTROL  
200  
300  
0
100  
400  
500  
600  
INPUT FREQUENCY (MHz)  
2224 TA01b  
2224 TA01  
ENCODE  
INPUT  
2224fa  
1

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