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LTC2223UK PDF预览

LTC2223UK

更新时间: 2024-11-26 05:43:43
品牌 Logo 应用领域
凌特 - Linear 转换器模数转换器
页数 文件大小 规格书
28页 824K
描述
12-Bit,105Msps/80Msps ADCs

LTC2223UK 数据手册

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LTC2222/LTC2223  
12-Bit,105Msps/  
80Msps ADCs  
U
FEATURES  
DESCRIPTIO  
The LTC®2222 and LTC2223 are 105Msps/80Msps, sam-  
pling 12-bit A/D converters designed for digitizing high  
frequency, wide dynamic range signals. The LTC2222/  
LTC2223 are perfect for demanding communications  
applicationswithACperformancethatincludes68dBSNR  
and 80dB spurious free dynamic range for signals  
up to 170MHz. Ultralow jitter of 0.15psRMS allows  
undersampling of IF frequencies with excellent noise  
performance.  
Sample Rate: 105Msps/80Msps  
68dB SNR up to 140MHz Input  
80dB SFDR up to 170MHz Input  
775MHz Full Power Bandwidth S/H  
Single 3.3V Supply  
Low Power Dissipation: 475mW/366mW  
Selectable Input Ranges: ±0.5V or ±1V  
No Missing Codes  
Optional Clock Duty Cycle Stabilizer  
Shutdown and Nap Modes  
DC specs include ±0.3LSB INL (typ), ±0.2LSB DNL (typ)  
Data Ready Output Clock  
and no missing codes over temperature. The transition  
Pin Compatible Family  
noise is a low 0.5LSBRMS  
.
135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit)  
105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit)  
80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit)  
Aseparateoutputpowersupplyallowstheoutputstodrive  
0.5V to 3.6V logic.  
The ENC+ and ENCinputs may be driven differentially or  
singleendedwithasinewave, PECL, LVDS, TTL, orCMOS  
inputs. An optional clock duty cycle stabilizer allows high  
performance at full speed for a wide range of clock duty  
cycles.  
48-Pin QFN Package  
U
APPLICATIO S  
Wireless and Wired Broadband Communication  
Cable Head-End Systems  
Power Amplifier Linearization  
Communications Test Equipment  
, LTC and LT are registered trademarks of Linear Technology Corporation.  
All other trademarks are the property of their respective owners.  
U
TYPICAL APPLICATIO  
V
DD  
3.3V  
SFDR vs Input Frequency  
100  
REFH  
REFL  
FLEXIBLE  
95  
REFERENCE  
4th OR HIGHER  
0V  
DD  
90  
85  
80  
75  
70  
65  
60  
0.5V TO 3.6V  
D11  
+
12-BIT  
PIPELINED  
ADC CORE  
CORRECTION  
LOGIC  
ANALOG  
INPUT  
OUTPUT  
DRIVERS  
INPUT  
S/H  
2nd or 3rd  
D0  
0GND  
CLOCK/DUTY  
CYCLE  
CONTROL  
0
200  
300  
400  
500  
22223 TA01b  
600  
100  
INPUT FREQUENCY (MHz)  
22201 TA01  
ENCODE  
INPUT  
22223fa  
1

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