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LTC2170IUKG-14#TRPBF PDF预览

LTC2170IUKG-14#TRPBF

更新时间： 2024-11-05 20:40:39
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
34页 1519K
描述
14-Bit, 25Msps Low Power Quad ADCs

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中文翻译

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LTC2170IUKG-14#TRPBF 数据手册

 浏览型号LTC2170IUKG-14#TRPBF的Datasheet PDF文件第2页浏览型号LTC2170IUKG-14#TRPBF的Datasheet PDF文件第3页浏览型号LTC2170IUKG-14#TRPBF的Datasheet PDF文件第4页浏览型号LTC2170IUKG-14#TRPBF的Datasheet PDF文件第5页浏览型号LTC2170IUKG-14#TRPBF的Datasheet PDF文件第6页浏览型号LTC2170IUKG-14#TRPBF的Datasheet PDF文件第7页 
LTC2172-14/  
LTC2171-14/LTC2170-14  
14-Bit, 65Msps/40Msps/  
25Msps Low Power Quad ADCs  
FeaTures  
DescripTion  
n
4-Channel Simultaneous Sampling ADC  
TheLTC®2172-14/LTC2171-14/LTC2170-14are4-channel,  
simultaneoussampling14-bitA/Dconvertersdesignedfor  
digitizinghighfrequency,widedynamicrangesignals.They  
are perfect for demanding communications applications  
with AC performance that includes 73.7dB SNR and 90dB  
spurious free dynamic range (SFDR). An ultralow jitter of  
n
73.7dB SNR  
n
90dB SFDR  
n
Low Power: 311mW/202mW/162mW Total,  
78mW/51mW/41mW per Channel  
Single 1.8V Supply  
n
n
Serial LVDS Outputs: One or Two Bits per Channel  
0.15ps  
allows undersampling of IF frequencies with  
RMS  
n
n
n
n
n
n
Selectable Input Ranges: 1V to 2V  
excellent noise performance.  
P-P  
P-P  
800MHz Full Power Bandwidth Sample-and-Hold  
DC specifications include 1LSB INL (typ), 0.3LSB DNL  
(typ) and no missing codes over temperature. The transi-  
tion noise is a low 1.2LSB  
Shutdown and Nap Modes  
Serial SPI Port for Configuration  
.
RMS  
Pin-Compatible 14-Bit and 12-Bit Versions  
52-Pin (7mm × 8mm) QFN Package  
The digital outputs are serial LVDS to minimize the num-  
ber of data lines. Each channel outputs two bits at a time  
(2-lanemode)oronebitatatime(1-lanemode).TheLVDS  
drivers have optional internal termination and adjustable  
output levels to ensure clean signal integrity.  
applicaTions  
n
Communications  
n
Cellular Base Stations  
+
–
n
Software Defined Radios  
The ENC and ENC inputs may be driven differentially  
or single-ended with a sine wave, PECL, LVDS, TTL or  
CMOS inputs. An internal clock duty cycle stabilizer al-  
lows high performance at full speed for a wide range of  
clock duty cycles.  
n
Portable Medical Imaging  
n
Multichannel Data Acquisition  
n
Nondestructive Testing  
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear  
Technology Corporation. All other trademarks are the property of their respective owners.  
Typical applicaTion  
1.8V  
V
1.8V  
OV  
LTC2172-14, 65Msps,  
DD  
DD  
2-Tone FFT, fIN = 70MHz and 75MHz  
CHANNEL 1  
ANALOG  
INPUT  
14-BIT  
OUT1A  
OUT1B  
0
–10  
–20  
–30  
–40  
S/H  
S/H  
S/H  
S/H  
ADC CORE  
CHANNEL 2  
ANALOG  
INPUT  
OUT2A  
OUT2B  
14-BIT  
ADC CORE  
DATA  
SERIALIZER  
–50  
SERIALIZED  
CHANNEL 3  
ANALOG  
INPUT  
OUT3A  
OUT3B  
14-BIT  
ADC CORE  
LVDS  
–60  
–70  
OUTPUTS  
–80  
–90  
CHANNEL 4  
ANALOG  
INPUT  
OUT4A  
OUT4B  
14-BIT  
ADC CORE  
–100  
–110  
–120  
DATA  
CLOCK  
OUT  
ENCODE  
INPUT  
PLL  
0
20  
10  
FREQUENCY (MHz)  
30  
FRAME  
217214 TA01b  
GND  
OGND  
217214 TA01  
21721014fb  
1
1234567...34

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