Electrical SpecificatiLonTsMSub9je0ct1to1C-h1an4g/e
LTM9010-14/LTM9009-14
14-Bit, 125Msps/105Msps/
80Msps Low Power Octal ADCs
FeaTures
DescripTion
The LTM®9011-14/LTM9010-14/LTM9009-14 are 8-channel,
simultaneous sampling 14-bit A/D converters designed
for digitizing high frequency, wide dynamic range signals.
AC performance includes 73.1dB SNR and 88dB spurious
free dynamic range (SFDR). Low power consumption per
channel reduces heat in high channel count applications.
Integrated bypass capacitance and flow-through pinout
reduces overall board space requirements.
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8-Channel Simultaneous Sampling ADC
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73.1dB SNR
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88dB SFDR
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Low Power: 140mW/113mW/94mW per Channel
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Single 1.8V Supply
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Serial LVDS Outputs: 1 or 2 Bits per Channel
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Selectable Input Ranges: 1V to 2V
P-P
P-P
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800MHz Full Power Bandwidth S/H
Shutdown and Nap Modes
DC specs include 1LSB INL (typ), 0.3LSB DNL (typ) and
no missing codes over temperature. The transition noise
Serial SPI Port for Configuration
Internal Bypass Capacitance, No External
Components
is a low 1.2LSB
.
RMS
The digital outputs are serial LVDS to minimize the num-
ber of data lines. Each channel outputs two bits at a time
(2-lane mode). At lower sampling rates there is a one bit
per channel option (1-lane mode).
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140-Pin (9mm × 11.25mm) BGA Package
applicaTions
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Communications
+
–
The ENC and ENC inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An internal clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
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Cellular Base Stations
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Software Defined Radios
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Portable Medical Imaging
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Multichannel Data Acquisition
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Nondestructive Testing
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
1.8V
1.8V
OV
LTM9011-14, 125Msps,
2-Tone FFT, fIN = 70MHz and 75MHz
V
DD
DD
CHANNEL 1
ANALOG
INPUT
0
–10
–20
–30
–40
14-BIT
OUT1A
OUT1B
S/H
S/H
ADC CORE
CHANNEL 2
ANALOG
INPUT
OUT2A
OUT2B
14-BIT
ADC CORE
DATA
SERIALIZER
–50
–60
–70
SERIALIZED
LVDS
OUTPUTS
CHANNEL 8
ANALOG
INPUT
OUT8A
OUT8B
14-BIT
ADC CORE
S/H
–80
–90
–100
–110
–120
DATA
CLOCK
OUT
ENCODE
INPUT
PLL
FRAME
0
20
30
40
50
60
10
FREQUENCY (MHz)
9009101114 TA01b
GND
OGND
9009101114 TA01
9009101114p
1