LTC2172-14/
LTC2171-14/LTC2170-14
14-Bit, 65Msps/40Msps/
25Msps Low Power Quad ADCs
FEATURES
DESCRIPTION
TheLTC®2172-14/LTC2171-14/LTC2170-14are4-channel,
simultaneoussampling14-bitA/Dconvertersdesignedfor
digitizinghighfrequency,widedynamicrangesignals.They
are perfect for demanding communications applications
with AC performance that includes 73.7dB SNR and 90dB
spurious free dynamic range (SFDR). An ultralow jitter of
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4-Channel Simultaneous Sampling ADC
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73.7dB SNR
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90dB SFDR
Low Power: 311mW/202mW/162mW Total,
78mW/51mW/41mW per Channel
Single 1.8V Supply
Serial LVDS Outputs: One or Two Bits per Channel
Selectable Input Ranges: 1V to 2V
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0.15ps
allows undersampling of IF frequencies with
RMS
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excellent noise performance.
P-P
P-P
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800MHz Full Power Bandwidth Sample-and-Hold
Shutdown and Nap Modes
DC specifications include 1LSB INL (typ), 0.3LSB DNL
(typ) and no missing codes over temperature. The transi-
tion noise is a low 1.2LSB
Serial SPI Port for Configuration
.
RMS
Pin-Compatible 14-Bit and 12-Bit Versions
52-Pin (7mm × 8mm) QFN Package
The digital outputs are serial LVDS to minimize the num-
ber of data lines. Each channel outputs two bits at a time
(2-lanemode)oronebitatatime(1-lanemode).TheLVDS
drivers have optional internal termination and adjustable
output levels to ensure clean signal integrity.
APPLICATIONS
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Communications
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Cellular Base Stations
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–
The ENC and ENC inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An internal clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
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Software Defined Radios
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Portable Medical Imaging
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Multichannel Data Acquisition
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Nondestructive Testing
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
1.8V
1.8V
OV
LTC2172-14, 65Msps,
2-Tone FFT, fIN = 70MHz and 75MHz
V
DD
DD
CHANNEL 1
ANALOG
INPUT
14-BIT
OUT1A
OUT1B
0
–10
–20
–30
–40
–50
S/H
S/H
S/H
S/H
ADC CORE
CHANNEL 2
ANALOG
INPUT
OUT2A
OUT2B
14-BIT
ADC CORE
DATA
SERIALIZER
SERIALIZED
CHANNEL 3
ANALOG
INPUT
OUT3A
OUT3B
14-BIT
ADC CORE
LVDS
–60
–70
OUTPUTS
–80
–90
–100
–110
–120
CHANNEL 4
ANALOG
INPUT
OUT4A
OUT4B
14-BIT
ADC CORE
DATA
CLOCK
OUT
ENCODE
INPUT
PLL
0
20
10
FREQUENCY (MHz)
30
FRAME
217214 TA01b
GND
OGND
217214 TA01
21721014f
1