LTC2162/LTC2161/LTC2160
16-Bit, 65Msps/
40Msps/25Msps
Low Power ADCs
DescripTion
FeaTures
The LTC®2162/LTC2161/LTC2160 are sampling 16-bit A/D
converters designed for digitizing high frequency, wide
dynamic range signals. They are perfect for demanding
communications applications with AC performance that
includes77dBSNRand90dBspuriousfreedynamicrange
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77dB SNR
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90dB SFDR
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Low Power: 87mW/63mW/4ꢀmW
Single 1.8V Supply
CMOS, DDR CMOS, or DDR LVDS Outputs
Selectable Input Ranges: 1V to 2V
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(SFDR).Ultralowjitterof0.07ps
allowsundersampling
P-P
P-P
RMS
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ꢀꢀ0MHz Full Power Bandwidth S/H
Optional Data Output Randomizer
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Serial SPI Port for Configuration
48-Pin (7mm × 7mm) QFN Package
of IF frequencies with excellent noise performance.
DC specs include 2LSB INL (typ), 0.ꢀLSB DNL (typ)
and no missing codes over temperature. The transition
noise is 3.3LSB
.
RMS
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
applicaTions
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+
–
Communications
The ENC and ENC inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
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Cellular Base Stations
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Software Defined Radios
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Portable Medical Imaging
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Multichannel Data Acquisition
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Nondestructive Testing
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
2-Tone FFT, fIN = 70MHz and 69MHz
1.8V
1.8V
OV
V
DD
DD
0
–10
–20
–30
–40
16-BIT
ADC CORE
ANALOG
INPUT
S/H
D15
•
•
•
D0
–50
–60
–70
CMOS
DDR CMOS OR
DDR LVDS
OUTPUTS
OUTPUT
DRIVERS
–80
–90
125MHz
CLOCK
CLOCK
CONTROL
–100
–110
–120
0
20
10
FREQUENCY (MHz)
30
216210 TA01a
2162 TA01b
GND
OGND
216210f
1