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LPC2926FBD144 PDF预览

LPC2926FBD144

更新时间： 2024-10-26 11:39:19
品牌 Logo 应用领域
恩智浦 - NXP 微控制器
页数 文件大小 规格书
95页 1867K
描述
ARM9 microcontroller with CAN, LIN, and USB

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LPC2926FBD144 技术参数

是否Rohs认证： 符合生命周期：Not Recommended
零件包装代码：QFP包装说明：LFQFP,
针数：144Reach Compliance Code：unknown
ECCN代码：3A991.A.2HTS代码：8542.31.00.01
风险等级：5.77具有ADC：YES
地址总线宽度：24位大小：32
最大时钟频率：40 MHzDAC 通道：NO
DMA 通道：YES外部数据总线宽度：32
JESD-30 代码：S-PQFP-G144JESD-609代码：e3
长度：20 mm湿度敏感等级：2
I/O 线路数量：104端子数量：144
最高工作温度：85 °C最低工作温度：-40 °C
PWM 通道：YES封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
认证状态：Not QualifiedROM可编程性：FLASH
座面最大高度：1.6 mm速度：125 MHz
最大供电电压：1.89 V最小供电电压：1.71 V
标称供电电压：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：20 mm
uPs/uCs/外围集成电路类型：MICROCONTROLLER, RISCBase Number Matches：1

LPC2926FBD144 数据手册

 浏览型号LPC2926FBD144的Datasheet PDF文件第2页浏览型号LPC2926FBD144的Datasheet PDF文件第3页浏览型号LPC2926FBD144的Datasheet PDF文件第4页浏览型号LPC2926FBD144的Datasheet PDF文件第5页浏览型号LPC2926FBD144的Datasheet PDF文件第6页浏览型号LPC2926FBD144的Datasheet PDF文件第7页 
LPC2926/2927/2929  
ARM9 microcontroller with CAN, LIN, and USB  
Rev. 5 — 28 September 2010  
Product data sheet  
1. General description  
The LPC2926/2927/2929 combine an ARM968E-S CPU core with two integrated TCM  
blocks operating at frequencies of up to 125 MHz, Full-speed USB 2.0 OTG and device  
controller, CAN and LIN, 56 kB SRAM, up to 768 kB flash memory, external memory  
interface, three 10-bit ADCs, and multiple serial and parallel interfaces in a single chip  
targeted at consumer, industrial and communication markets. To optimize system power  
consumption, the LPC2926/2927/2929 has a very flexible Clock Generation Unit (CGU)  
that provides dynamic clock gating and scaling.  
2. Features and benefits  
„ ARM968E-S processor running at frequencies of up to 125 MHz maximum.  
„ Multi-layer AHB system bus at 125 MHz with four separate layers.  
„ On-chip memory:  
‹ Two Tightly Coupled Memories (TCM), 32 kB Instruction TCM (ITCM), 32 kB Data  
TCM (DTCM).  
‹ Two separate internal Static RAM (SRAM) instances; 32 kB SRAM and 16 kB  
SRAM.  
‹ 8 kB ETB SRAM also available for code execution and data.  
‹ Up to 768 kB high-speed flash-program memory.  
‹ 16 kB true EEPROM, byte-erasable and programmable.  
„ Dual-master, eight-channel GPDMA controller on the AHB multi-layer matrix which can  
be used with the Serial Peripheral Interface (SPI) interfaces and the UARTs, as well as  
for memory-to-memory transfers including the TCM memories.  
„ External Static Memory Controller (SMC) with eight memory banks; up to 32-bit data  
bus; up to 24-bit address bus.  
„ Serial interfaces:  
‹ USB 2.0 full-speed device/OTG controller with dedicated DMA controller and  
on-chip device PHY.  
‹ Two-channel CAN controller supporting FullCAN and extensive message filtering.  
‹ Two LIN master controllers with full hardware support for LIN communication. The  
LIN interface can be configured as UART to provide two additional UART  
interfaces.  
‹ Two 550 UARTs with 16-byte Tx and Rx FIFO depths, DMA support, and  
RS485/EIA-485 (9-bit) support.  
‹ Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep;  
Tx FIFO and Rx FIFO.  
‹ Two I2C-bus interfaces.  
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