Datasheet > LPC2927_10

LPC2927_10

更新时间： 2024-10-26 05:42:35

品牌	Logo	应用领域
恩智浦 - NXP		微控制器
页数	文件大小	规格书
95页	615K
描述
ARM9 microcontroller with CAN, LIN, and USB

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LPC2927_10 数据手册

LPC2927/2929

ARM9 microcontroller with CAN, LIN, and USB

Rev. 04 — 14 April 2010

Product data sheet

1. General description

The LPC2927/2929 combine an ARM968E-S CPU core with two integrated TCM blocks

operating at frequencies of up to 125 MHz, Full-speed USB 2.0 OTG and device

controller, CAN and LIN, 56 kB SRAM, up to 768 kB flash memory, external memory

interface, three 10-bit ADCs, and multiple serial and parallel interfaces in a single chip

targeted at consumer, industrial and communication markets. To optimize system power

consumption, the LPC2927/2929 has a very flexible Clock Generation Unit (CGU) that

provides dynamic clock gating and scaling.

2. Features and benefits

ARM968E-S processor running at frequencies of up to 125 MHz maximum.

Multi-layer AHB system bus at 125 MHz with four separate layers.

On-chip memory:

Two Tightly Coupled Memories (TCM), 32 kB Instruction TCM (ITCM), 32 kB Data

TCM (DTCM).

Two separate internal Static RAM (SRAM) instances; 32 kB SRAM and 16 kB

SRAM.

8 kB ETB SRAM also available for code execution and data.

Up to 768 kB high-speed flash-program memory.

16 kB true EEPROM, byte-erasable and programmable.

Dual-master, eight-channel GPDMA controller on the AHB multi-layer matrix which can

be used with the Serial Peripheral Interface (SPI) interfaces and the UARTs, as well as

for memory-to-memory transfers including the TCM memories.

External Static Memory Controller (SMC) with eight memory banks; up to 32-bit data

bus; up to 24-bit address bus.

Serial interfaces:

USB 2.0 full-speed device/OTG controller with dedicated DMA controller and

on-chip device PHY.

Two-channel CAN controller supporting FullCAN and extensive message filtering.

Two LIN master controllers with full hardware support for LIN communication. The

LIN interface can be configured as UART to provide two additional UART

interfaces.

Two 550 UARTs with 16-byte Tx and Rx FIFO depths, DMA support, and

RS485/EIA-485 (9-bit) support.

Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep;

Tx FIFO and Rx FIFO.

Two I²C-bus interfaces.

12 3 4 5 6 7...95

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