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LMK01010ISQ/NOPB PDF预览

LMK01010ISQ/NOPB

更新时间: 2024-11-18 21:06:03
品牌 Logo 应用领域
美国国家半导体 - NSC 驱动输出元件逻辑集成电路
页数 文件大小 规格书
22页 368K
描述
IC 01010 SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC48, 7 X 7 MM, 0.80 MM HEIGHT, LLP-48, Clock Driver

LMK01010ISQ/NOPB 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:HVQCCN, LCC48,.27SQ,20Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.22系列:01010
输入调节:DIFFERENTIALJESD-30 代码:S-XQCC-N48
JESD-609代码:e3长度:7 mm
逻辑集成电路类型:CLOCK DRIVER最大I(ol):0.0005 A
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:48
实输出次数:8最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC48,.27SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.03 ns座面最大高度:0.8 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.45 V
最小供电电压 (Vsup):3.15 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7 mm
Base Number Matches:1

LMK01010ISQ/NOPB 数据手册

 浏览型号LMK01010ISQ/NOPB的Datasheet PDF文件第2页浏览型号LMK01010ISQ/NOPB的Datasheet PDF文件第3页浏览型号LMK01010ISQ/NOPB的Datasheet PDF文件第4页浏览型号LMK01010ISQ/NOPB的Datasheet PDF文件第5页浏览型号LMK01010ISQ/NOPB的Datasheet PDF文件第6页浏览型号LMK01010ISQ/NOPB的Datasheet PDF文件第7页 
July 15, 2009  
LMK01000 Family  
LMK01000 Family 1.6 GHz High Performance Clock Buffer,  
Divider, and Distributor  
General Description  
Features  
The LMK01000 family provides an easy way to divide and  
distribute high performance clock signals throughout the sys-  
tem. These devices provide best-in-class noise performance  
and are designed to be pin-to-pin and footprint compatible  
with LMK03000/LMK02000 family of precision clock condi-  
tioners.  
30 fs additive jitter (100 Hz to 20 MHz)  
Dual clock inputs  
Programmable output channels (0 to 1600 MHz)  
External synchronization  
Pin compatible family of clocking devices  
3.15 to 3.45 V operation  
The LMK01000 family features two programmable clock in-  
puts (CLKin0 and CLKin1) that allow the user to dynamically  
switch between different clock domains.  
Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)  
LVDS  
Outputs  
LVPECL  
Outputs  
Each device features 8 clock outputs with independently pro-  
grammable dividers and delay adjustments. The outputs of  
the device can be easily synchronized by an external pin  
(SYNC*).  
Device  
LMK01000  
LMK01010  
LMK01020  
3
8
0
5
0
8
Target Applications  
High performance Clock Distribution  
Wireless Infrastructure  
Medical Imaging  
Wired Communications  
Test and Measurement  
Military / Aerospace  
System Diagram  
30042806  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 2009 National Semiconductor Corporation  
300428  
www.national.com  

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