Datasheet > LMK01801BISQ

LMK01801BISQ

更新时间： 2024-09-27 11:46:03

品牌	Logo	应用领域
德州仪器 - TI		时钟
页数	文件大小	规格书
39页	487K
描述
Dual Clock Divider Buffer

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LMK01801BISQ 数据手册

January 16, 2012

LMK01801

Dual Clock Divider Buffer

1.0 General Description

The LMK01801 is a very low noise solution for clocking sys-

tems that require distribution and frequency division of preci-

sion clocks.

The LMK01801 features extremely low residual noise, fre-

quency division, digital and analog delay adjustments, and

fourteen (14) programmable differential outputs: LVPECL,

LVDS and LVCMOS (2 outputs per differential output).

3.0 Features

Pin control mode or MICROWIRE (SPI)

■

Input and Output Frequency Range 1 kHz to 3.1 GHz

Separate Input for Clock Output Banks A & B.

14 Differential Clock Outputs in Two Banks (A & B)

■

Output Bank A

—

8 Differential, programmable outputs (Up to 8 as

LVCMOS)

■

The LMK01801 features two independent inputs that can be

driven differentially (LVDS, LVPECL) or in single-ended mode

(LVCMOS, RF Sinewave). The first input drives output Bank

A consisting of eight (8) outputs. The second input drives out-

put Bank B consisting of six (6) outputs.

Divider Values of 1 to 8, Even and Odd.

■

Output Bank B

—

6 Differential Outputs (or up to 12 as LVCMOS)

■

Divides values of 1 to 1045 or 1 to 8, even and odd

Analog and Digital Delays

2.0 Target Applications

50% duty cycle on all outputs for all divides

Separate Synchronization of Bank A and B.

RMS Additive jitter 50 fs at 800 MHz

■

•

High performance clock distribution and division

Wireless infrastructure

Datacom and telecom clock distribution

Medical imaging

Test and measurement

Military / Aerospace

50 fs RMS Additive jitter (12 kHz to 20 MHz)

—

Industrial Temperature Range: -40 to 85 °C

■

3.15 V to 3.45 V operation

Package: 48-pin LLP (7.0 x 7.0 x 0.8 mm)

30148701

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

PLLatinum™ is a trademark of National Semiconductor Corporation.

301487 SNAS573

www.ti.com

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与LMK01801BISQ相关器件

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LMK01801BISQ/NOPB	TI	获取价格	双路时钟分配 \| RHS \| 48 \| -40 to 85
LMK01801BISQE	TI	获取价格	Dual Clock Divider Buffer
LMK01801BISQE/NOPB	TI	获取价格	双路时钟分配 \| RHS \| 48 \| -40 to 85
LMK01801BISQX	TI	获取价格	Dual Clock Divider Buffer
LMK01801BISQX/NOPB	TI	获取价格	双路时钟分配 \| RHS \| 48 \| -40 to 85
LMK02000	TI	获取价格	selecting amplifiers, adcs, and clocks for high-performance signal paths
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