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LMK01010ISQX PDF预览

LMK01010ISQX

更新时间: 2024-11-18 03:51:43
品牌 Logo 应用领域
美国国家半导体 - NSC 时钟
页数 文件大小 规格书
18页 432K
描述
1.6 GHz High Performance Clock Buffer, Divider, and Distributor

LMK01010ISQX 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:7 X 7 MM, 0.80 MM HEIGHT, LLP-48Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.23
系列:01010输入调节:DIFFERENTIAL
JESD-30 代码:S-XQCC-N48JESD-609代码:e0
长度:7 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
最大I(ol):0.0005 A湿度敏感等级:2
功能数量:1反相输出次数:
端子数量:48实输出次数:8
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC48,.27SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
电源:3.3 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.03 ns座面最大高度:0.8 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.45 V
最小供电电压 (Vsup):3.15 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
宽度:7 mmBase Number Matches:1

LMK01010ISQX 数据手册

 浏览型号LMK01010ISQX的Datasheet PDF文件第2页浏览型号LMK01010ISQX的Datasheet PDF文件第3页浏览型号LMK01010ISQX的Datasheet PDF文件第4页浏览型号LMK01010ISQX的Datasheet PDF文件第5页浏览型号LMK01010ISQX的Datasheet PDF文件第6页浏览型号LMK01010ISQX的Datasheet PDF文件第7页 
March 6, 2008  
LMK01000/LMK01010/LMK01020  
1.6 GHz High Performance Clock Buffer, Divider, and  
Distributor  
General Description  
Features  
The LMK01000/LMK01010/LMK01020 family provides an  
easy way to divide and distribute high performance clock sig-  
nals throughout the system. These devices provide best-in-  
class noise performance and are designed to be pin-to-pin  
and footprint compatible with LMK03000/LMK02000 family of  
precision clock conditioners.  
30 fs additive jitter (100 Hz to 20 MHz)  
Dual clock inputs  
Programmable output channels (0 to 1600 MHz)  
LMK01000: 3 LVDS outputs (CLKout0 - CLKout2) + 5  
LVPECL outputs (CLKout3 - CLKout7)  
LMK01010: 8 LVDS outputs  
The LMK01000/LMK01010/LMK01020 family features two  
programmable clock inputs (CLKin0 and CLKin1) that allow  
the user to dynamically switch between different clock do-  
mains.  
LMK01020: 8 LVPECL outputs  
Channel divider values of 1, 2 to 510 (even divides)  
Programmable output skew control  
Each device features 8 clock outputs with independently pro-  
grammable dividers and delay adjustments. The outputs of  
the device can be easily synchronized by an external pin  
(SYNC*).  
External synchronization  
Pin compatible family of clocking devices  
3.15 to 3.45 V operation  
Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)  
Target Applications  
High performance Clock Distribution  
Wireless Infrastructure  
Medical Imaging  
Wired Communications  
Test and Measurement  
Military / Aerospace  
System Diagram  
30042806  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 2008 National Semiconductor Corporation  
300428  
www.national.com  

LMK01010ISQX 替代型号

型号 品牌 替代类型 描述 数据表
LMK01010ISQ NSC

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