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LMK00725 PDF预览

LMK00725

更新时间: 2024-01-17 07:52:19
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
23页 1006K
描述
Low Skew, 1-to-5, Differential-to-3.3V LVPECL Fanout Buffer

LMK00725 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP20,.25针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:6 weeks风险等级:5.74
系列:00725输入调节:DIFFERENTIAL MUX
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:6.5 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:20
实输出次数:10最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TR峰值回流温度(摄氏度):260
电源:3.3 V最大电源电流(ICC):60 mA
Prop。Delay @ Nom-Sup:0.37 ns传播延迟(tpd):0.37 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.035 ns
座面最大高度:1.2 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mm最小 fmax:650 MHz
Base Number Matches:1

LMK00725 数据手册

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LMK00725  
www.ti.com  
SNAS625A SEPTEMBER 2013REVISED OCTOBER 2013  
Low Skew, 1-to-5, Differential-to-3.3V LVPECL Fanout Buffer  
Check for Samples: LMK00725  
1
FEATURES  
APPLICATIONS  
Five 3.3V Differential LVPECL Outputs  
Wireless and Wired Infrastructure  
Networking and Data Communications  
Servers and Computing  
Additive Jitter: 43 fs RMS (typ) @ 312.5  
MHz  
Noise Floor (1 MHz offset): -158 dBc/Hz  
Medical Imaging  
(typ) @ 312.5 MHz  
Portable Test and Measurement  
High-End A/V  
Output Frequency: 650 MHz (max)  
Output Skew: 35 ps (max)  
Part-to-Part Skew: 100 ps (max)  
Propagation Delay: 0.37 ns (max)  
DESCRIPTION  
The LMK00725 is a low skew, high-performance  
clock fanout buffer which can distribute up to five  
3.3V LVPECL outputs from one of two inputs, which  
can accept differential or single-ended inputs. The  
clock enable input is synchronized internally to  
eliminate runt or glitch pulses on the outputs when  
the clock enable pin is asserted or de-asserted. The  
low additive jitter and phase noise floor and ensured  
output and part-to-part skew characteristics make the  
LMK00725 ideal for applications demanding high  
performance and repeatability.  
Two Differential Input Pairs (pin-selectable)  
CLKx, nCLK Input Pairs can accept  
LVPECL, LVDS, HCSL, SSTL, LVHSTL, or  
Single-Ended Signals  
Synchronous Clock Enable  
Power Supply: 3.3V ± 5%  
Package: 20-Lead TSSOP  
Industrial Temperature Range: -40ºC to +85ºC  
FUNCTIONAL BLOCK DIAGRAM  
RPU  
CLK_EN  
D
Q
RPD  
RPU  
RPD  
RPU  
CLK0  
0
1
nCLK0  
Q0  
CLK1  
nQ0  
Q1  
nCLK1  
nQ1  
Q2  
RPD  
CLK_SEL  
nQ2  
Q3  
RPU = Pullup  
RPD = Pulldown  
nQ3  
Q4  
nQ4  
(1) RPU = 51 kΩ pullup, RPD = 51 kΩ pulldown  
Figure 1.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2013, Texas Instruments Incorporated  
 
 

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