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LMK00725PW PDF预览

LMK00725PW

更新时间: 2024-11-18 12:36:35
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
23页 1006K
描述
Low Skew, 1-to-5, Differential-to-3.3V LVPECL Fanout Buffer

LMK00725PW 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP-20针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:1.71系列:00725
输入调节:DIFFERENTIAL MUXJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:6.5 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:20实输出次数:10
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TUBE
峰值回流温度(摄氏度):260电源:3.3 V
最大电源电流(ICC):60 mAProp。Delay @ Nom-Sup:0.37 ns
传播延迟(tpd):0.37 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.035 ns座面最大高度:1.2 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
最小 fmax:650 MHzBase Number Matches:1

LMK00725PW 数据手册

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LMK00725  
www.ti.com  
SNAS625A SEPTEMBER 2013REVISED OCTOBER 2013  
Low Skew, 1-to-5, Differential-to-3.3V LVPECL Fanout Buffer  
Check for Samples: LMK00725  
1
FEATURES  
APPLICATIONS  
Five 3.3V Differential LVPECL Outputs  
Wireless and Wired Infrastructure  
Networking and Data Communications  
Servers and Computing  
Additive Jitter: 43 fs RMS (typ) @ 312.5  
MHz  
Noise Floor (1 MHz offset): -158 dBc/Hz  
Medical Imaging  
(typ) @ 312.5 MHz  
Portable Test and Measurement  
High-End A/V  
Output Frequency: 650 MHz (max)  
Output Skew: 35 ps (max)  
Part-to-Part Skew: 100 ps (max)  
Propagation Delay: 0.37 ns (max)  
DESCRIPTION  
The LMK00725 is a low skew, high-performance  
clock fanout buffer which can distribute up to five  
3.3V LVPECL outputs from one of two inputs, which  
can accept differential or single-ended inputs. The  
clock enable input is synchronized internally to  
eliminate runt or glitch pulses on the outputs when  
the clock enable pin is asserted or de-asserted. The  
low additive jitter and phase noise floor and ensured  
output and part-to-part skew characteristics make the  
LMK00725 ideal for applications demanding high  
performance and repeatability.  
Two Differential Input Pairs (pin-selectable)  
CLKx, nCLK Input Pairs can accept  
LVPECL, LVDS, HCSL, SSTL, LVHSTL, or  
Single-Ended Signals  
Synchronous Clock Enable  
Power Supply: 3.3V ± 5%  
Package: 20-Lead TSSOP  
Industrial Temperature Range: -40ºC to +85ºC  
FUNCTIONAL BLOCK DIAGRAM  
RPU  
CLK_EN  
D
Q
RPD  
RPU  
RPD  
RPU  
CLK0  
0
1
nCLK0  
Q0  
CLK1  
nQ0  
Q1  
nCLK1  
nQ1  
Q2  
RPD  
CLK_SEL  
nQ2  
Q3  
RPU = Pullup  
RPD = Pulldown  
nQ3  
Q4  
nQ4  
(1) RPU = 51 kΩ pullup, RPD = 51 kΩ pulldown  
Figure 1.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2013, Texas Instruments Incorporated  
 
 

LMK00725PW 替代型号

型号 品牌 替代类型 描述 数据表
LMK00725PWR TI

完全替代

Low Skew, 1-to-5, Differential-to-3.3V LVPECL Fanout Buffer

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