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LMH1983SQ/NOPB PDF预览

LMH1983SQ/NOPB

更新时间： 2024-11-19 11:14:35
品牌 Logo 应用领域
德州仪器 - TI 时钟外围集成电路晶体时钟发生器
页数 文件大小 规格书
55页 1943K
描述
具有音频时钟的 3G/高清/标清视频时钟发生器 | RTA | 40 | -40 to 85

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中文翻译

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LMH1983SQ/NOPB 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：HVQCCN, LCC40,.24SQ,20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：1.29JESD-30 代码：S-PQCC-N40
JESD-609代码：e3长度：6 mm
湿度敏感等级：3端子数量：40
最高工作温度：85 °C最低工作温度：-40 °C
最大输出时钟频率：148.5 MHz封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装等效代码：LCC40,.24SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：3.3 V
主时钟/晶体标称频率：27 MHz认证状态：Not Qualified
座面最大高度：0.8 mm子类别：Clock Generators
最大压摆率：212 mA最大供电电压：3.465 V
最小供电电压：3.135 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, VIDEO
Base Number Matches：1

LMH1983SQ/NOPB 数据手册

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Sample &  
Buy  
Support &  
Community  
Product  
Folder  
Tools &  
Software  
Technical  
Documents  
LMH1983  
SNLS309I –APRIL 2010–REVISED DECEMBER 2014  
LMH1983 3G/HD/SD Video Clock Generator with Audio Clock  
1 Features  
3 Description  
The LMH1983 is a highly-integrated programmable  
1
•
Four PLLs for Simultaneous A/V Clock Generation  
audio/video (A/V) clock generator intended for  
broadcast and professional applications. It can  
replace multiple PLLs and VCXOs used in  
applications supporting SMPTE serial digital video  
(SDI) and digital audio AES3/EBU standards. It offers  
low-jitter reference clocks for any SDI transmitter to  
meet stringent output jitter specifications without  
additional clock cleaning circuits.  
–
–
–
–
PLL1: 27 or 13.5 MHz  
PLL2: 148.5 or 74.25 MHz  
PLL3: 148.5/1.001 or 74.25/1.001 MHz  
PLL4: 98.304 MHz / 2X (X = 0 to 15)  
•
•
3 x 2 Video Clock Crosspoint  
Flexible PLL Bandwidth to Optimize Jitter  
Performance and Lock Time  
The LMH1983 features automatic input format  
detection, simple programming of multiple A/V output  
formats, genlock or digital free-run modes, and  
override programmability of various automatic  
functions. The recognized input formats include HVF  
syncs for the major video standards, 27 MHz, 10  
MHz, and 32/44.1/48/96 kHz audio word clocks.  
•
•
•
Soft Resynchronization to New Reference  
Digital Holdover or Free-run on Loss of Reference  
Status Flags for Loss of Reference and Loss of  
PLL Lock  
•
•
3.3 V Single Supply Operation  
I2C Interface with Address Select Pin (3 States)  
The dual-stage PLL architecture integrates four PLLs  
with three on-chip VCOs. The first stage (PLL1) uses  
an external low-noise 27 MHz VCXO with narrow  
loop bandwidth to provide a clean reference clock for  
the next stage. The second stage (PLL2, 3, 4)  
consists of three parallel VCO PLLs for simultaneous  
generation of the major digital A/V clock fundamental  
rates, including 148.5 MHz, 148.5/1.001 MHz, and  
98.304 MHz (4 × 24.576 MHz). Each PLL can  
generate a clock and a timing pulse to indicate top of  
frame (TOF).  
2 Applications  
•
•
•
•
•
•
•
•
•
•
Triple Rate (3G/HD/SD) SDI SerDes  
FPGA Reference Clock Generation/Cleaning  
Audio Embed or De-embed  
Video Cameras  
Frame Synchronizers (Genlock, DARS)  
A-D or D-A Conversion, Editing, Processing Cards  
Keyers and Logo Inserters  
Device Information(1)  
Format or Standards Converters  
Video Displays and Projectors  
PART NUMBER  
PACKAGE  
BODY SIZE (NOM)  
LMH1983  
WQFN (40)  
6.00 mm × 6.00 mm  
A/V Test and Measurement Equipment  
(1) For all available packages, see the orderable addendum at  
the end of the datasheet.  
Typical Application Block Diagram  
LOOP  
FILTER  
27 MHz  
VCXO  
27 MHz (PLL1)  
525i  
Analog  
ref. in  
H sync  
V sync  
F sync  
CLKout1  
29.97 Hz (TOF1)  
525i/29.97 SDI out  
+ embedded audio  
LMH1981  
Sync  
Separator  
Hin  
Vin  
Fin  
148.5 MHz (PLL2)  
29.97 Hz (TOF2)  
CLKout2  
CLKout3  
FPGA  
1080p/59.94 SDI out  
+ embedded audio  
A/V Frame Sync with  
Downconverter,  
LMH1983  
148.35 MHz (PLL3)  
59.94 Hz (TOF3)  
Audio Embedder and  
De-embedder  
1080p/59.94 SDI in  
+ embedded audio  
24.576 MHz (PLL4)  
5.994 Hz  
CLKout4  
Genlocked to video ref. in  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
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