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LMH1982SQE

更新时间： 2024-01-12 21:44:11
品牌 Logo 应用领域
美国国家半导体 - NSC 时钟发生器
页数 文件大小 规格书
28页 504K
描述
Multi-Rate Video Clock Generator with Genlock

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中文翻译

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LMH1982SQE 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：LLP-32Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.17
系列：1982输入调节：STANDARD
JESD-30 代码：S-XQCC-N32JESD-609代码：e0
长度：5 mm逻辑集成电路类型：PLL BASED CLOCK DRIVER
湿度敏感等级：1功能数量：1
反相输出次数：端子数量：32
实输出次数：1最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
认证状态：Not Qualified座面最大高度：0.8 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD宽度：5 mm
Base Number Matches：1

LMH1982SQE 数据手册

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PRELIMINARY  
April 9, 2008  
LMH1982  
Multi-Rate Video Clock Generator with Genlock  
General Description  
Features  
The LMH1982 is a multi-rate video clock generator ideal for  
use in a wide range of 3-Gbps (3G), high-definition (HD), and  
standard-definition (SD) video applications, such as video  
synchronization, serial digital interface (SDI) serializer and  
deserializer (SerDes), video conversion, video editing, and  
other broadcast and professional video systems.  
Two simultaneous LVDS output clocks with selectable  
■
frequencies and Hi-Z capability:  
SD clock: 27 MHz or 67.5 MHz  
—
—
HD clock: 74.25 MHz, 74.25/1.001 MHz, 148.5 MHz or  
148.5/1.001 MHz  
Low-jitter output clocks may be directly connected to an  
FPGA serializer to meet SMPTE SDI jitter specifications  
Top of Frame (TOF) pulse with programmable output  
format timing and Hi-Z capability  
■
■
The LMH1982 can generate two simultaneous SD and HD  
clocks and a Top of Frame (TOF) pulse. In genlock mode, the  
device's phase locked loops (PLLs) can synchronize the out-  
put signals to H sync and V sync input signals applied to either  
of the reference ports. The input reference can have analog  
timing from National's LMH1981 multi-format video sync sep-  
arator or digital timing from an SDI deserializer and should  
conform to the major SD and HD standards. When a loss of  
reference occurs, the device can default to free run operation  
where the output timing accuracy will be determined by the  
external bias on the free run control voltage input.  
Two reference ports (A and B) with H and V sync inputs  
Supports cross-locking of input and output timing  
■
■
■
External loop filter allows control of loop bandwidth, jitter  
transfer, and lock time characteristics  
Free run or Holdover operation on loss of reference  
User-defined free run control voltage input  
I2C interface and control registers  
■
■
■
■
The LMH1982 can replace discrete PLLs and field-pro-  
grammable gate array (FPGA) PLLs with multiple voltage  
controlled crystal oscillators (VCXOs). Only one 27.0000 MHz  
VCXO and loop filter are externally required for genlock  
mode. The external loop filter as well as programmable PLL  
parameters can provide narrow loop bandwidths to minimize  
jitter transfer. HD clock output jitter as low as 40 ps peak-to-  
peak can help designers using FPGA serializers meet strin-  
gent SDI output jitter specifications.  
3.3V and 2.5V supplies  
Applications  
Video genlock and synchronization  
■
■
■
■
Triple rate 3G/HD/SD-SDI SerDes  
Video capture, conversion, editing and distribution  
Video displays and projectors  
Broadcast and professional video equipment  
The LMH1982 is offered in a space-saving 5 mm x 5 mm 32-  
pin LLP package and provides low total power dissipation of  
250 mW (typical).  
■
Typical System Block Diagram  
30052410  
© 2008 National Semiconductor Corporation  
300524  
www.national.com  
1234567...28

中文翻译

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