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LMH1982

更新时间: 2024-11-19 11:07:51
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动时钟驱动器时钟发生器
页数 文件大小 规格书
43页 1028K
描述
具有同步锁相的多速率视频时钟发生器

LMH1982 数据手册

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LMH1982  
www.ti.com  
SNLS289C APRIL 2008REVISED MARCH 2013  
LMH1982 Multi-Rate Video Clock Generator with Genlock  
Check for Samples: LMH1982  
1
FEATURES  
DESCRIPTION  
The LMH1982 is a multi-rate video clock generator  
ideal for use in a wide range of 3-Gbps (3G), high-  
definition (HD), and standard-definition (SD) video  
applications, such as video synchronization, serial  
digital interface (SDI) serializer and deserializer  
(SerDes), video conversion, video editing, and other  
broadcast and professional video systems.  
2
Two Simultaneous LVDS Output Clocks with  
Selectable Frequencies and Hi-Z Capability:  
SD Clock: 27 MHz or 67.5 MHz  
HD Clock: 74.25 MHz, 74.25/1.001 MHz,  
148.5 MHz or 148.5/1.001 MHz  
Low-Jitter Output Clocks May Be Directly  
Connected to an FPGA Serializer to Meet  
SMPTE SDI Jitter Specifications  
The LMH1982 can generate two simultaneous SD  
and HD clocks and a Top of Frame (TOF) pulse. In  
genlock mode, the device's phase locked loops  
(PLLs) can synchronize the output signals to H sync  
and V sync input signals applied to either of the  
reference ports. The input reference can have analog  
timing from Texas Instrument's LMH1981 multi-format  
video sync separator or digital timing from an SDI  
deserializer and should conform to the major SD and  
HD standards. When a loss of reference occurs, the  
device can default to free run operation where the  
output timing accuracy will be determined by the  
external bias on the free run control voltage input.  
Top of Frame (TOF) Pulse with Programmable  
Output Format Timing and Hi-Z Capability  
Two reference ports (A and B) with H and V  
sync inputs  
Supports Cross-Locking of Input and Output  
Timing  
External Loop Filter Allows Control of Loop  
Bandwidth, Jitter Transfer, and Lock Time  
Characteristics  
Free Run or Holdover Operation on Loss of  
Reference  
The LMH1982 can replace discrete PLLs and field-  
programmable gate array (FPGA) PLLs with multiple  
voltage controlled crystal oscillators (VCXOs). Only  
one 27.0000 MHz VCXO and loop filter are externally  
required for genlock mode. The external loop filter as  
well as programmable PLL parameters can provide  
narrow loop bandwidths to minimize jitter transfer. HD  
clock output jitter as low as 40 ps peak-to-peak can  
help designers using FPGA SerDes meet stringent  
SDI output jitter specifications.  
User-Defined Free Run Control Voltage Input  
I2C Interface and Control Registers  
3.3V and 2.5V Supplies  
APPLICATIONS  
Video Genlock and Synchronization  
FPGA SDI SerDes Recovered Clock  
Generation  
The LMH1982 is offered in a space-saving 5 mm x 5  
mm 32-pin WQFN package and provides low total  
power consumption of about 250 mW (typical).  
Triple Rate 3G/HD/SD-SDI SerDes  
Video Capture, Conversion, Editing and  
Distribution  
Video Displays and Projectors  
Broadcast and Professional Video Equipment  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2008–2013, Texas Instruments Incorporated  

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