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LMH0318

更新时间： 2023-09-03 20:28:08
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动驱动器
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57页 1214K
描述
具有集成电缆驱动器的 3G HD/SD SDI 时钟恢复器

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LMH0318  
www.ti.com.cn  
ZHCSE54 –SEPTEMBER 2015  
Pin Descriptions – SMBUS Mode/ MODE_SEL = 1 kΩ to GND  
PIN  
I/O  
DESCRIPTION  
NAME  
NO.  
1
Determines Device Configuration: SPI or SMBus  
1 kΩ to GND: SMBUS mode. See Initialization Set Up  
MODE_SEL  
ADDR0  
Input, 4-Level  
2
4-level strap pins used to set the SMBus address of the device. The pin  
state is read on power-up. The multi-level nature of these pins allows for  
16 unique device addresses. Note SMBus section for further details. The  
four strap options include:  
1 kΩ to VDD:  
•
Represents logic state 11’b  
Input, 4-Level  
ADDR1  
15  
Float(Default): Represents logic state 10'b 7-bits SMBus address = 0x17  
20 kΩ to GND:  
•
Represents logic state 01'b  
1 kΩ to GND:  
•
Represents logic state 00'b  
SMBus clock input / open drain. External 2-kΩ to 5-kΩ pull-up resistor is  
required as per SMBus interface standard. This pin is 3.3 V LVCMOS  
tolerant.  
SCL  
3
4
Input, 2-Level  
SMBus data input / open drain. External 2-kΩ to 5-kΩ pull-up resistor is  
required as per SMBus interface standard. This pin is 3.3 V LVCMOS  
tolerant.  
I/O, Open Drain, 2-  
Level  
SDA  
5,14,17,  
18  
RESERVED  
No Connect  
Powers down device when pulled low  
1 kΩ to VDD:  
•
Power down until valid signal detected  
Float(Default): Reserved  
20 kΩ to GND:  
ENABLE  
6
Input, 4-Level  
•
Reserved  
1 kΩ to GND:  
Power down including signal detects and Reset Registers upon  
power-up  
•
Output, LVCMOS Programmable Interrupt caused by change in LOS, violation of internal  
LOS_INT_N  
LOCK  
13  
16  
Open Drain, 2-  
Level  
eye monitor threshold, change in lock. External 4.7-kΩ pull-up resistor is  
required. This pin is 3.3 V LVCMOS tolerant.  
Indicates CDR lock Status  
High:  
Output, 2.5 V  
LVCMOS, 2-Level  
•
CDR locked  
Low:  
•
CDR not locked  
HIGH SPEED DIFFERENTIAL I/O  
IN0+  
11  
12  
8
Input, Analog  
Input, Analog  
Input, Analog  
Input, Analog  
Inverting and non-inverting differential inputs. An on-chip 100 Ω  
terminating resistor connects IN0+ to IN0-. Inputs require 4.7 µF AC  
coupling capacitors.  
IN0-  
IN1+  
IN1-  
Inverting and non-inverting differential inputs. An on-chip 100 Ω  
terminating resistor connects IN0+ to IN0-. Inputs require 4.7 µF AC  
coupling capacitors.  
9
Output, 75 Ω CML  
OUT0+  
OUT0-  
20  
19  
Inverting and non-inverting 75 Ω outputs. An on-chip 75 Ω terminating  
resistor connects OUT0+ and OUT0- to VDD. Outputs require 4.7 µF AC  
coupling capacitors  
Compatible  
Output, 75 Ω CML  
Compatible  
OUT1+  
OUT1-  
23  
22  
Output, Analog  
Output, Analog  
Inverting and non-inverting differential outputs. An on-chip 100 Ω  
terminating resistor connects OUT1+ to OUT1-. Outputs require 4.7 µF AC  
coupling capacitors  
VDD  
VSS  
DAP  
7, 21  
2.5 V Supply  
Ground  
2.5V ± 5%  
10, 24  
Connect directly to ground (GND)  
Exposed DAP, connect to GND using at least 5 vias (see 图 23 )  
Ground  
Copyright © 2015, Texas Instruments Incorporated  
5
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