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LMH0341SQE/NOPB

更新时间： 2024-02-08 00:05:02
品牌 Logo 应用领域
德州仪器 - TI 接口集成电路
页数 文件大小 规格书
33页 505K
描述
具有环路输出和 LVDS 接口的 3G HD/SD DVB-ASI SDI 解串器 | RHS | 48 | -40 to 85

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LMH0341SQE/NOPB 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN,针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.07差分输出：NO
输入特性：STANDARD接口集成电路类型：LINE RECEIVER
接口标准：GENERAL PURPOSEJESD-30 代码：S-PQCC-N48
JESD-609代码：e3长度：7 mm
湿度敏感等级：3功能数量：6
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C最小输出摆幅：2.7 V
封装主体材料：PLASTIC/EPOXY封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260认证状态：Not Qualified
最大接收延迟：接收器位数：6
座面最大高度：0.8 mm最大压摆率：127 mA
最大供电电压：2.625 V最小供电电压：2.375 V
标称供电电压：2.5 V电源电压1-最大：3.465 V
电源电压1-分钟：3.135 V电源电压1-Nom：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7 mm
Base Number Matches：1

LMH0341SQE/NOPB 数据手册

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LMH0041, LMH0051  
LMH0071, LMH0341  
www.ti.com  
SNLS272Q –APRIL 2007–REVISED APRIL 2013  
3 Gbps, HD, SD, DVB-ASI SDI Deserializer with Loopthrough and LVDS Interface  
Check for Samples: LMH0041, LMH0051, LMH0071, LMH0341  
1
FEATURES  
DESCRIPTION  
The LMH0341/0041/0071/0051 SDI Deserializers are  
part of TI’s family of FPGA-Attach SER/DES products  
supporting 5-bit LVDS interfaces with FPGAs. When  
paired with a host FPGA the LMH0341 automatically  
detects the incoming data rate and decodes the raw  
5-bit data words compliant to any of the following  
standards: DVB-ASI, SMPTE 259M, SMPTE 292M,  
or SMPTE 424M. See Table 1 for details on which  
Standards are supported per device.  
23  
•
5-Bit LVDS Interface  
•
•
No External VCO or Clock Required  
Reclocked Serial Loopthrough With Cable  
Driver  
•
•
•
•
Powerdown Mode  
3.3V SMBus Configuration Interface  
Small 48-Pin WQFN Package  
Industrial Temperature range: -40°C to +85°C  
The interface between the LMH0341 and the host  
FPGA consists of a 5-bit wide LVDS bus, an LVDS  
clock and an SMBus interface. No external VCOs or  
clocks are required. The LMH0341 CDR detects the  
frequency from the incoming data stream, generates  
a clean clock and transmits both clock and data to  
the host FPGA. The LMH0341, LMH0041 and  
LMH0071 include a serial reclocked loopthrough with  
integrated SMPTE compliant cable driver. Refer to  
Table 1 for a complete listing of single channel  
deserializers offered in this family.  
APPLICATIONS  
•
SDI Interfaces for:  
–
–
–
–
Video Cameras  
DVRs  
Video Switchers  
Video Editing Systems  
KEY SPECIFICATIONS  
The FPGA-Attach SER/DES product family is  
supported by a suite of IP which allows the design  
engineer to quickly develop video applications using  
the SER/DES products. The product is packaged in a  
physically small 48 pin WQFN package.  
•
•
•
Output compliant with SMPTE 259M-C, SMPTE  
292M, SMPTE 424M and DVB-ASI (See Table 1)  
Typical power dissipation: 590 mW  
(loopthrough disabled, 3G datarate)  
0.6 UI Minimum Input Jitter Tolerance  
General Block Diagram  
RESET  
LOCK  
GPIO[2:0]  
SDA  
DVB_ASI  
Loopthru_EN  
Control  
SMBus  
SCK  
SMB_CS  
RXCLK  
RX4  
RX_MUX_SEL  
RXIN0  
RXIN1  
RX3  
CLK  
CDR  
Data  
MUX  
RX2  
RX1  
TXOUT  
RX0  
LVDS Drivers  
SMPTE Cable Driver  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
TRI-STATE is a registered trademark of National Semiconductor Corporation.  
2
3
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2007–2013, Texas Instruments Incorporated  
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