October 5, 2009
LMH0341, LMH0041,
LMH0071, LMH0051
3 Gbps, HD, SD, DVB-ASI SDI Deserializer with
Loopthrough and LVDS Interface
General Description
Key Specifications
The LMH0341/0041/0071/0051 SDI Deserializers are part of
National’s family of FPGA-Attach SER/DES products sup-
porting 5-bit LVDS interfaces with FPGAs. When paired with
a host FPGA the LMH0341 automatically detects the incom-
ing data rate and decodes the raw 5-bit data words compliant
to any of the following standards: DVB-ASI, SMPTE 259M,
SMPTE 292M, or SMPTE 424M. See Table 1 for details on
which Standards are supported per device.
Output compliant with SMPTE 259M-C, SMPTE 292M,
SMPTE 424M and DVB-ASI (See Table 1)
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Typical power dissipation: 590 mW (loopthrough disabled,
3G datarate)
0.6 UI Minimum Input Jitter Tolerance
Features
5–bit LVDS Interface
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The interface between the LMH0341 and the host FPGA con-
sists of a 5-bit wide LVDS bus, an LVDS clock and an SMBus
interface. No external VCOs or clocks are required. The
LMH0341 CDR detects the frequency from the incoming data
stream, generates a clean clock and transmits both clock and
data to the host FPGA. The LMH0341, LMH0041 and
LMH0071 include a serial reclocked loopthrough with inte-
grated SMPTE compliant cable driver. Refer to table 1 for a
complete listing of single channel deserializers offered in this
family.
No external VCO or clock required
Reclocked serial loopthrough with Cable Driver
Powerdown Mode
3.3V SMBus configuration interface
Small 48 pin LLP package
Industrial Temperature range:-40°C to +85°C
Applications
The FPGA-Attach SER/DES product family is supported by a
suite of IP which allows the design engineer to quickly develop
video applications using the SER/DES products. The product
is packaged in a physically small 48 pin LLP package.
SDI interfaces for:
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Video Cameras
DVRs
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Video Switchers
Video Editing Systems
General Block Diagram
30017201
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