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LMD18200_05 PDF预览

LMD18200_05

更新时间: 2024-10-28 03:51:39
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
14页 878K
描述
3A, 55V H-Bridge

LMD18200_05 数据手册

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Switching Time Definitions  
01056809  
Pin 11, BOOTSTRAP 2 Input: Bootstrap capacitor pin for  
Half H-bridge number 2. The recommended capacitor  
(10 nF) is connected between pins 10 and 11.  
Pinout Description  
(See Connection Diagram)  
Pin 1, BOOTSTRAP 1 Input: Bootstrap capacitor pin for half  
H-bridge number 1. The recommended capacitor (10 nF) is  
connected between pins 1 and 2.  
TABLE 1. Logic Truth Table  
Pin 2, OUTPUT 1: Half H-bridge number 1 output.  
PWM  
Dir  
H
L
Brake  
Active Output Drivers  
Source 1, Sink 2  
Sink 1, Source 2  
Source 1, Source 2  
Source 1, Source 2  
Sink 1, Sink 2  
Pin 3, DIRECTION Input: See Table 1. This input controls  
the direction of current flow between OUTPUT 1 and OUT-  
PUT 2 (pins 2 and 10) and, therefore, the direction of rotation  
of a motor load.  
H
H
L
L
L
X
L
H
H
L
H
L
H
H
H
Pin 4, BRAKE Input: See Table 1. This input is used to  
brake a motor by effectively shorting its terminals. When  
braking is desired, this input is taken to a logic high level and  
it is also necessary to apply logic high to PWM input, pin 5.  
The drivers that short the motor are determined by the logic  
level at the DIRECTION input (Pin 3): with Pin 3 logic high,  
both current sourcing output transistors are ON; with Pin 3  
logic low, both current sinking output transistors are ON. All  
output transistors can be turned OFF by applying a logic high  
to Pin 4 and a logic low to PWM input Pin 5; in this case only  
a small bias current (approximately −1.5 mA) exists at each  
output pin.  
X
NONE  
Application Information  
TYPES OF PWM SIGNALS  
The LMD18200 readily interfaces with different forms of  
PWM signals. Use of the part with two of the more popular  
forms of PWM is described in the following paragraphs.  
Simple, locked anti-phase PWM consists of a single, vari-  
able duty-cycle signal in which is encoded both direction and  
amplitude information (see Figure 2). A 50% duty-cycle  
PWM signal represents zero drive, since the net value of  
voltage (integrated over one period) delivered to the load is  
zero. For the LMD18200, the PWM signal drives the direc-  
tion input (pin 3) and the PWM input (pin 5) is tied to logic  
high.  
Pin 5, PWM Input: See Table 1. How this input (and DIREC-  
TION input, Pin 3) is used is determined by the format of the  
PWM Signal.  
Pin 6, VS Power Supply  
Pin 7, GROUND Connection: This pin is the ground return,  
and is internally connected to the mounting tab.  
Pin 8, CURRENT SENSE Output: This pin provides the  
sourcing current sensing output signal, which is typically  
377 µA/A.  
Pin 9, THERMAL FLAG Output: This pin provides the  
thermal warning flag output signal. Pin 9 becomes active-low  
at 145˚C (junction temperature). However the chip will not  
shut itself down until 170˚C is reached at the junction.  
Pin 10, OUTPUT 2: Half H-bridge number 2 output.  
www.national.com  
6

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