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LMD18200_05

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LMD18200_05 数据手册

Application Information (Continued)

SIGNAL TRANSITION REQUIREMENTS

To ensure proper internal logic performance, it is good prac-

tice to avoid aligning the falling and rising edges of input

signals. A delay of at least 1 µsec should be incorporated

between transitions of the Direction, Brake, and/or PWM

input signals. A conservative approach is be sure there is at

least 500ns delay between the end of the first transition and

the beginning of the second transition. See Figure 4.

01056804

FIGURE 2. Locked Anti-Phase PWM Control

Sign/magnitude PWM consists of separate direction (sign)

and amplitude (magnitude) signals (see Figure 3). The (ab-

solute) magnitude signal is duty-cycle modulated, and the

absence of a pulse signal (a continuous logic low level)

represents zero drive. Current delivered to the load is pro-

portional to pulse width. For the LMD18200, the DIRECTION

input (pin 3) is driven by the sign signal and the PWM input

(pin 5) is driven by the magnitude signal.

01056805

FIGURE 3. Sign/Magnitude PWM Control

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型号	品牌	描述	获取价格	数据表
LMD18200_13	TI	LMD18200 3A, 55V H-Bridge	获取价格
LMD18200_15	TI	3A, 55V H-Bridge	获取价格
LMD18200-2D/883	NSC	3A, 55V H-Bridge	获取价格
LMD18200-2D/883	TI	2.4A, 55V H-Bridge	获取价格
LMD18200-2D-MPR	NSC	IC 6 A HB BASED PRPHL DRVR WITH PWM, CDIP24, CERDIP-24, Peripheral Driver	获取价格
LMD18200-2D-QV	NSC	3A, 55V H-Bridge	获取价格