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LM98620

更新时间: 2024-11-14 11:13:11
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
71页 1144K
描述
具有 LVDS 输出的 10 位 70 MSPS 6 通道图像信号处理器

LM98620 数据手册

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LM98620  
SNAS426C FEBRUARY 2008REVISED MAY 2014  
LM98620 10-Bit 70 MSPS 6 Channel Imaging Signal Processor with LVDS Output  
1 Features  
2 Applications  
1
3.3 V Single Supply Operation  
CDS or S/H Processing  
35 MHz Channel Rate  
High Performance Digital Color Copiers  
Scanners  
Other Image Processing Applications  
Enhanced ESD Protection on Timing, Control and  
LVDS Pins  
3 Description  
The LM98620 is a fully integrated, 10-Bit, 70 MSPS  
signal processing solution for high performance digital  
color copiers, scanners, and other image processing  
applications. High-speed signal throughput is  
achieved with an innovative six channel architecture  
utilizing Correlated Double Sampling (CDS), or  
Sample and Hold (SH) type sampling. Gain settings  
of 1x or 2x are available in the CDS/SH input stage.  
Each channel has a dedicated 1x to 10x (8 bit) PGA  
that allows accurate gain adjustment. The Digital  
White Level auto calibration loop can automatically  
set the PGA value to achieve a selected white target  
level. Each channel also has a ±4 bit coarse and ±10-  
bit fine analog offset correction DAC that allows offset  
correction before the sample-and-hold amplifier.  
These correction values can be controlled by an  
automated Digital Black Level correction loop. The  
PGA and offset DACs for each channel are  
programmed independently allowing unique values of  
gain and offset for each of the six channels. A 2-to-1  
multiplexing scheme routes the signals to three 70  
MHz high performance ADCs. The fully differential  
processing channels achieve exceptional noise  
immunity, having a very low noise floor of –68.5dB.  
The 10-bit analog-to-digital converters have excellent  
dynamic performance, making the LM98620  
transparent in the image reproduction chain.  
Low Power CMOS Design  
12 Terminal to 16 Terminal (Selectable) LVDS  
Serialized Data Output  
4-Wire Serial Interface  
2 Channel Symmetrical Architecture  
Independent Gain and Offset Correction for Each  
Channel  
Digital Black Level Calibration for Each Channel  
Digital White Level Calibration for Each Channel  
Programmable Input Clamp  
Key Specifications  
Maximum Input Level:  
1.2 Vp-p (CDS Gain = 1.0)  
0.58 Vp-p (CDS Gain = 2.1)  
Input Sample Rate:  
5 to 35 MSPS - 6ch mode  
10 to 35 MSPS - 3ch mode  
PGA Gain Range: 1x to 10x (0 to 20 dB)  
CDS/SH Gain Settings: 1x or 2.1x  
Total Channel Gain: 1x to 21x (0 to 26 dB)  
PGA Gain Resolution: 8 bits - Analog  
ADC Resolution: 10 bits  
Device Information(1)  
ADC Sampling Rate: 10 to 70 MSPS  
SNR: 68.5 dB (Gain = 1x)  
PART NUMBER  
PACKAGE  
BODY SIZE (NOM)  
LM98620  
TQFP (80)  
12.00 mm × 12.00 mm  
Offset DAC Range:  
(1) For all available packages, see the orderable addendum at  
the end of the datasheet.  
±111 mV or ±59.5 mV - FDAC  
±281 mV - CDAC  
Simplified Schematic  
Offset DAC Resolution:  
Red  
±10 bits - FDAC  
±4 bits - CDAC  
CDAC  
+/- 4  
FDAC  
+/- 10  
1x or 2.1 x gain  
Black Level Loop  
White Level Loop  
Supply Voltage: 3.0 V to 3.6 V  
8
8
CDS/  
SH  
OSR1  
OSR2  
™
™
PGA  
PGA  
Power Dissipation: 1.02 W (typical)  
M
U
X
10  
10  
ADC  
CDS/  
SH  
Black Level Loop  
White Level Loop  
+/- 10  
+/- 4  
FDAC  
CDAC  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 

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