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LM98722 PDF预览

LM98722

更新时间: 2024-09-25 05:42:23
品牌 Logo 应用领域
美国国家半导体 - NSC 时钟发生器传感器
页数 文件大小 规格书
14页 453K
描述
3 Channel, 16-Bit, 45 MSPS Analog Front End with LVDS/CMOS Output, Integrated CCD/CIS Sensor Timing Generator and Spread Spectrum Clock Generation

LM98722 数据手册

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September 24, 2009  
LM98722  
3 Channel, 16-Bit, 45 MSPS Analog Front End with LVDS/  
CMOS Output, Integrated CCD/CIS Sensor Timing  
Generator and Spread Spectrum Clock Generation  
General Description  
Features  
The LM98722 is a fully integrated, high performance 16-Bit,  
45 MSPS signal processing solution for digital color copiers,  
scanners, and other image processing applications. High-  
speed signal throughput is achieved with an innovative archi-  
tecture utilizing Correlated Double Sampling (CDS), typically  
employed with CCD arrays, or Sample and Hold (S/H) inputs  
(for higher speed CCD or CMOS image sensors). The signal  
paths utilize 8 bit Programmable Gain Amplifiers (PGA), a  
+/-9-Bit offset correction DAC and independently controlled  
Digital Black Level correction loops for each input. The PGA  
and offset DAC are programmed independently allowing  
unique values of gain and offset for each of the three analog  
inputs. The signals are then routed to a 45MHz high perfor-  
mance analog-to-digital converter (ADC). The fully differential  
processing channel shows exceptional noise immunity, hav-  
ing a very low noise floor of -74dB. The 16-bit ADC has  
excellent dynamic performance making the LM98722 trans-  
parent in the image reproduction chain.  
LVDS/CMOS Outputs  
LVDS/CMOS/Crystal Clock Source with PLL Multiplication  
Integrated Flexible Spread Spectrum Clock Generation  
CDS or S/H Processing for CCD or CIS sensors  
Independent Gain/Offset Correction for Each Channel  
Automatic per-Channel Gain and Offset Calibration  
Programmable Input Clamp Voltage  
Flexible CCD/CIS Sensor Timing Generator  
Key Specifications  
Maximum Input Level  
1.2 or 2.4 Volt Modes  
(both with + or - polarity option)  
16-Bit  
ADC Resolution  
ADC Sampling Rate  
INL  
45 MSPS  
+18/-25 LSB (typ)  
22.5/22.5/15 MSPS  
256 Steps  
Channel Sampling Rate  
PGA Gain Steps  
PGA Gain Range  
Analog DAC Resolution  
Analog DAC Range  
Digital DAC Resolution  
Digital DAC Range  
SNR  
A very flexible integrated Spread Spectrum Clock Generation  
(SSCG) modulator is included to assist with EM compliance  
and reduce system costs.  
0.64 to 8.3x  
+/-9 Bits  
+/-307mV or +/-614mV  
+/-6 Bits  
Applications  
Multi-Function Peripherals  
-2048 LSB to + 2016 LSB  
-74dB (@0dB PGA Gain)  
630mW (LVDS)  
0 to 70°C  
High-speed Currency/Check Scanners  
Flatbed or Handheld Color Scanners  
Power Dissipation  
Operating Temp  
Supply Voltage  
High-speed Document Scanners  
3.3V Nominal (3.0V to 3.6V range)  
System Block Diagram  
30099570  
© 2009 National Semiconductor Corporation  
300995  
www.national.com  

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