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LM98620 PDF预览

LM98620

更新时间: 2024-11-13 11:50:51
品牌 Logo 应用领域
英飞凌 - INFINEON /
页数 文件大小 规格书
6页 154K
描述
10-bit 70 MSPS 6 Channel Imaging Signal Processor with 10-bit 70 MSPS 6 Channel Imaging Signal Processor with

LM98620 数据手册

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February 21, 2008  
LM98620  
10-bit 70 MSPS 6 Channel Imaging Signal Processor with  
LVDS Output  
General Description  
The LM98620 is a fully integrated, 10-Bit, 70 MSPS signal  
4-Wire Serial interface  
Low Power CMOS Design  
12 pin to 16 pin (selectable) LVDS serialized data output  
processing solution for high performance digital color copiers,  
scanners, and other image processing applications. High-  
speed signal throughput is achieved with an innovative six  
channel architecture utilizing Correlated Double Sampling  
(CDS), or Sample and Hold (SH) type sampling. 1x or 2x gain  
settings are available in the CDS/SH input stage. Each chan-  
nel has a dedicated 1x to 10x (8 bit) PGA that allows accurate  
gain adjustment of each channel. The Digital White Level auto  
calibration loop can automatically set the PGA value to  
achieve a selected white target level. Each channel also has  
a ±4 bit coarse and ±10-bit fine analog offset correction DAC  
that allows offset correction before the sample-and-hold am-  
plifier. These correction values can be controlled by an auto-  
mated Digital Black Level correction loop. The PGA and offset  
DACs for each channel are programmed independently al-  
lowing unique values of gain and offset for each of the six  
channels. A 2-to-1 multiplexing scheme routes the signals to  
three 70MHz high performance ADCs. The fully differential  
processing channels achieve exceptional noise immunity,  
having a very low noise floor of -68.5dB. The 10-bit analog-  
to-digital converters have excellent dynamic performance  
making the LM98620 transparent in the image reproduction  
chain.  
2 Channel Symmetrical Architecture  
Independent Gain and Offset Correction for each Channel  
Digital Black Level Calibration for each Channel  
Digital White Level Calibration for each Channel  
Programmable Input Clamp  
Key Specifications  
Maximum Input Level  
1.2 Vp-p (CDS gain = 1.0)  
0.58 Vp-p (CDS gain = 2.0)  
5 to 35 MSPS - 6ch mode  
10 to 35 MSPS - 3ch mode  
1x to 10x (0 to 20 dB)  
1x or 2.1x  
Input Sample Rate  
PGA Gain Range  
CDS/SH Gain Settings  
Total Channel Gain  
PGA Gain Resolution  
ADC Resolution  
ADC Sampling Rate  
SNR  
Offset DAC Range  
1x to 21x (0 to 26 dB)  
8 bits - Analog  
10 bits  
10 to 70 MSPS  
68.5 dB (Gain = 1x)  
±111 mV or ±59.5 mV- FDAC  
±281 mV - CDAC  
±10 bits - FDAC  
Offset DAC Resolution  
Features  
±4 bits - CDAC  
3.0V to 3.6V  
1.02 W (typical)  
Supply voltage  
Power Dissipation  
3.3V Single Supply Operation  
CDS or S/H Processing  
35 MHz Channel Rate  
Enhanced ESD Protection on Timing, Control and LVDS  
Pins  
System Block Diagram  
30032304  
© 2008 National Semiconductor Corporation  
300323  
www.national.com  

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