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LF412MWC PDF预览

LF412MWC

更新时间: 2024-11-26 19:54:19
品牌 Logo 应用领域
美国国家半导体 - NSC 放大器
页数 文件大小 规格书
11页 485K
描述
IC DUAL OP-AMP, 3000 uV OFFSET-MAX, 4 MHz BAND WIDTH, UUC8, WAFER, Operational Amplifier

LF412MWC 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:WAFER包装说明:DIE, WAFER
针数:8Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.33.00.01
风险等级:5.44放大器类型:OPERATIONAL AMPLIFIER
架构:VOLTAGE-FEEDBACK最大平均偏置电流 (IIB):0.0002 µA
25C 时的最大偏置电流 (IIB):0.0002 µA标称共模抑制比:100 dB
频率补偿:YES最大输入失调电流 (IIO):0.025 µA
最大输入失调电压:3000 µVJESD-30 代码:R-XUUC-N8
低-偏置:YES低-失调:NO
湿度敏感等级:1负供电电压上限:-18 V
标称负供电电压 (Vsup):-15 V功能数量:2
端子数量:8最高工作温度:70 °C
最低工作温度:封装主体材料:UNSPECIFIED
封装代码:DIE封装等效代码:WAFER
封装形状:RECTANGULAR封装形式:UNCASED CHIP
峰值回流温度(摄氏度):260电源:+-15 V
认证状态:Not Qualified筛选级别:MIL-STD-883
最小摆率:8 V/us标称压摆率:15 V/us
子类别:Operational Amplifier最大压摆率:6.5 mA
供电电压上限:18 V标称供电电压 (Vsup):15 V
表面贴装:YES技术:BIPOLAR
温度等级:COMMERCIAL端子形式:NO LEAD
端子位置:UPPER处于峰值回流温度下的最长时间:40
标称均一增益带宽:4000 kHz最小电压增益:15000
Base Number Matches:1

LF412MWC 数据手册

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April 1999  
LF412  
Low Offset, Low Drift Dual JFET Input Operational  
Amplifier  
General Description  
Features  
n Internally trimmed offset voltage: 1 mV (max)  
n Input offset voltage drift: 10 µV/˚C (max)  
n Low input bias current: 50 pA  
These devices are low cost, high speed, JFET input opera-  
tional amplifiers with very low input offset voltage and guar-  
anteed input offset voltage drift. They require low supply cur-  
rent yet maintain a large gain bandwidth product and fast  
slew rate. In addition, well matched high voltage JFET input  
devices provide very low input bias and offset currents.  
LF412 dual is pin compatible with the LM1558, allowing de-  
signers to immediately upgrade the overall performance of  
existing designs.  
n Low input noise current:  
n Wide gain bandwidth: 3 MHz (min)  
n High slew rate: 10V/µs (min)  
n Low supply current: 1.8 mA/Amplifier  
n High input impedance: 1012Ω  
n Low total harmonic distortion AV 10,: 0.02%  
=
These amplifiers may be used in applications such as high  
speed integrators, fast D/A converters, sample and hold cir-  
cuits and many other circuits requiring low input offset volt-  
age and drift, low input bias current, high input impedance,  
high slew rate and wide bandwidth.  
=
=
=
RL 10k, VO 20 Vp-p, BW 20 Hz-20 kHz  
n Low 1/f noise corner: 50 Hz  
n Fast settling time to 0.01%: 2 µs  
Typical Connection  
Connection Diagrams  
Metal Can Package  
DS005656-42  
Order Number LF412AMH, LF412MH,  
LF412CH or LF412MH/883 (Note 1)  
See NS Package Number H08A  
DS005656-41  
Ordering Information  
LF412XYZ  
X
Y
indicates electrical grade  
indicates temperature range  
“M” for military  
Dual-In-Line Package  
“C” for commercial  
indicates package type  
“H” or “N”  
Z
DS005656-44  
Order Number LF412ACN, LF412CN  
or LF412MJ/883 (Note 1)  
See NS Package Number J08A or N08E  
BI-FET II is a trademark of National Semiconductor Corporation.  
© 1999 National Semiconductor Corporation  
DS005656  
www.national.com  

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