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LF43168GC15 PDF预览

LF43168GC15

更新时间: 2024-11-04 19:53:03
品牌 Logo 应用领域
逻辑 - LOGIC 时钟LTE输入元件外围集成电路
页数 文件大小 规格书
16页 292K
描述
Digital Filter, 10-Bit, CMOS, CPGA84, CERAMIC, PGA-84

LF43168GC15 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:PGA包装说明:PGA, PGA84M,11X11
针数:84Reach Compliance Code:unknown
ECCN代码:3A001.A.3HTS代码:8542.39.00.01
风险等级:5.7其他特性:2 X 10 BIT DATA INPUT BUS; ICC SPECIFIED @ 20MHZ
边界扫描:NO最大时钟频率:66.7 MHz
外部数据总线宽度:10JESD-30 代码:S-CPGA-P84
JESD-609代码:e0长度:29.464 mm
低功率模式:NO湿度敏感等级:3
端子数量:84最高工作温度:70 °C
最低工作温度:输出数据总线宽度:28
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:PGA
封装等效代码:PGA84M,11X11封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):225
电源:5 V认证状态:Not Qualified
座面最大高度:4.445 mm子类别:DSP Peripherals
最大压摆率:300 mA最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:PIN/PEG端子节距:2.54 mm
端子位置:PERPENDICULAR处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:29.464 mmuPs/uCs/外围集成电路类型:DSP PERIPHERAL, DIGITAL FILTER
Base Number Matches:1

LF43168GC15 数据手册

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LF43168  
Dual 8-Tap FIR Filter  
DEVICES INCORPORATED  
FEATURES  
DESCRIPTION  
The LF43168 is a high-speed dual FIR  
filter capable of filtering data at real-  
time video rates. The device contains  
two FIR filters which may be used as  
two separate filters or cascaded to  
form one filter. The input and coeffi-  
cient data are both 10-bits and can be  
in unsigned, two’s complement, or  
mixed mode format.  
be implemented. The LF43168 can  
decimate the output data by as much  
as 16:1. When the device is pro-  
grammed to decimate, the number of  
clock cycles available to calculate filter  
taps increases. When configured for  
16:1 decimation, each filter can be  
configured as a 128-tap FIR filter (if  
symmetric coefficient sets are used).  
By cascading these two filters, the  
device can be configured as a 256-tap  
FIR filter.  
66 MHz Data and Computation Rate  
Two Independent 8-Tap or Single  
16-Tap FIR Filters  
10-bit Data and Coefficient Inputs  
32 Programmable Coefficient Sets  
Supports Interleaved Coefficient Sets  
User Programmable Decimation up  
to 16:1  
Maximum of 256 FIR Filter Taps,  
16 x 16 2-D Kernels, or 10 x 20-bit  
Data and Coefficients  
The filter architecture is optimized for  
symmetric coefficient sets. When  
symmetric coefficient sets are used,  
Replaces Harris HSP43168  
each filter can be configured as an 8-tap There is on-chip storage for 32  
Package Styles Available:  
• 84-pin Plastic LCC, J-Lead  
• 100-pin Plastic Quad Flatpack  
• 84-pin Ceramic PGA  
FIR filter. If the two filters are cas-  
caded, a 16-tap FIR filter can be  
implemented. When asymmetric  
coefficient sets are used, each filter is  
different sets of coefficients. Each set  
consists of eight coefficients. Access  
to more than one coefficient set  
facilitates adaptive filtering opera-  
configured as a 4-tap FIR filter. If both tions. The 28-bit filter output can be  
filters are cascaded, an 8-tap filter can rounded from 8 to 19 bits.  
LF43168 BLOCK DIAGRAM  
INB9-0  
/
10  
OUT8-0  
9
10  
INA9-0  
5
10  
9
CSEL4-0  
CIN9-0  
A
8-0  
WR  
COEFFICIENT  
BANK A  
FILTER  
CELL A  
COEFFICIENT  
BANK B  
FILTER  
CELL B  
CONTROL  
MUX/ADDER  
9
19  
OUT27-9  
OEL  
OEH  
Video Imaging Products  
03/22/1999–LDS.43168-G  
1

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