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LF3311QC9 PDF预览

LF3311QC9

更新时间： 2024-11-29 14:52:03
品牌 Logo 应用领域
逻辑 - LOGIC 时钟LTE外围集成电路
页数 文件大小 规格书
24页 622K
描述
Digital Filter, 12-Bit, CMOS, PQFP144, PLASTIC, QFP-144

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中文翻译

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LF3311QC9 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Contact Manufacturer零件包装代码：QFP
包装说明：QFP,针数：144
Reach Compliance Code：compliantECCN代码：3A001.A.3
HTS代码：8542.39.00.01风险等级：5.2
Is Samacsys：N边界扫描：NO
最大时钟频率：111.11 MHz外部数据总线宽度：12
JESD-30 代码：S-PQFP-G144长度：28 mm
低功率模式：NO湿度敏感等级：3
端子数量：144最高工作温度：70 °C
最低工作温度：输出数据总线宽度：12
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装形状：SQUARE封装形式：FLATPACK
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：4.0995 mm最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：28 mm
uPs/uCs/外围集成电路类型：DSP PERIPHERAL, DIGITAL FILTERBase Number Matches：1

LF3311QC9 数据手册

 浏览型号LF3311QC9的Datasheet PDF文件第2页浏览型号LF3311QC9的Datasheet PDF文件第3页浏览型号LF3311QC9的Datasheet PDF文件第4页浏览型号LF3311QC9的Datasheet PDF文件第5页浏览型号LF3311QC9的Datasheet PDF文件第6页浏览型号LF3311QC9的Datasheet PDF文件第7页 
LF3311  
Horizontal / Vertical Digital Image Filter  
DEVICES INCORPORATED  
Improved Performance  
FEATURES  
8 Vertical Filter Taps  
111 MHz Data Rate  
Two Operating Modes: Dimensionally Sepa-  
rate and Orthogonal  
12-bit Data and Coefficients  
On-board Memory for 256 Horizontal and 256 Verti-  
cal Coefficient Sets  
Supports Interleaved Data Streams  
Horizontal Filter Supports Decimation up to  
16:1 for Increasing Number of Filter Taps  
LF Interface™ Allows All 512 Coefficient Sets to be  
Updated Within Vertical Blanking  
3.3 Volt Power Supply  
5 Volt Tolerant I/O  
144 Lead PQFP  
Selectable 12-bit Data Output with User-Defined  
Rounding and Limiting  
Seven 3K x 12-bit, Programmable Two-Mode Line  
Buffers  
16 Horizontal Filter Taps  
DESCRIPTION  
The LF3311 is an improved version of the LF3310 Horizontal/Vertical Digital Image Filter capable of  
operating at speeds of up to 111MHz. This improved speed will increase flexibility and performance. The  
added performance will enable you to use this device in more applications. For example, four interleaved  
data streams of 27MHz can now be processed within one device. The part is functionally identical to the  
LF3320 with the exception that the filter data path is specified to operate faster than the LF Control Interface.  
When operating the filter at speeds in excess of 90MHz, loading of coefficients via the LF Interface must  
be throttled to a maximum of 90MHz by asserting the PAUSE pin as required to allow sufficient setup time  
for the configuration data provided to the Figure 1 below demonstrates the switching waveforms of case 2,  
while the switching characteristics are shown in Table 1.  
Figure 1. Switching Waveforms: LF InterfaceTM  
CLK  
tPWL  
tPWH  
tS0  
tLH  
tCYC  
LDA  
LDB  
tPS  
tPH  
PAUSEA  
PAUSEB  
tCFH  
tCFS  
ADDRESS  
CFA 11-0  
CFB 11-0  
CF0  
CF1  
The LF3311 remains a two-dimensional digital image filter capable of filtering data at real-time video rates.  
The device contains both a horizontal and a vertical filter which may be cascaded or used concurrently for  
two-dimensional filtering. The input, coefficient, and output data are all 12-bits and in two’s complement  
format. The horizontal filter is designed to take advantage of symmetric coefficient sets. When symmetric  
coefficient sets are used, the horizontal filter can be configured as a 16-tap FIR filter. When asymmetric  
coefficient sets are used, it can be configured as an 8-tap FIR filter. The vertical filter is an 8-tap FIR  
filter with all required line buffers contained on-chip. The line buffers can store video lines with lengths  
from 4 to 3076 pixels. Horizontal filter Interleave/Decimation Registers (I/D Registers) and the vertical filter  
line buffers allow interleaved data to be fed directly into the device and filtered without separating the data  
into individual data streams. The horizontal filter can handle a maximum of sixteen data sets interleaved  
together. The vertical filter can handle interleaved video lines which contain 3076 or less data values. The  
I/D Registers and horizontal accumulator facilitate using decimation to increase the number of filter taps  
in the horizontal filter. It will support a decimation factor of up to 16:1. The device has on-chip storage  
for 256 horizontal coefficient sets and 256 vertical coefficient sets. Each filter’s coefficients are loaded  
independently of each other allowing one filter’s coefficients to be updated without affecting the other filter’s  
coefficients. In addition, a horizontal or vertical coefficient set can be updated independently from the other  
coefficient sets in the same filter.  
Video Imaging Products  
LOGIC Devices Incorporated  
1
Dec 18, 2001 LDS.3311-A  
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