Datasheet > LF3320QC15G

LF3320QC15G

更新时间： 2024-11-30 04:08:19

品牌	Logo	应用领域
逻辑 - LOGIC		/
页数	文件大小	规格书
24页	1050K
描述
Digital Filter, 12-Bit, CMOS, PQFP144, GREEN, PLASTIC, QFP-144

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LF3320QC15G 数据手册

LF3320

DEVICES INCORPORATED

Horizontal Digital Image Filter

LF3320

Horizontal Digital Image Filter

FEATURES

DESCRIPTION

ꢀ 83 MHz Data Rate

ꢀ 12-bit Data or Coefficients (Expand-

The LF3320 filters digital images in

the horizontal dimension at real-time

Interleave/Decimation Registers (I/D

Registers) allow interleaved data to be

video rates. The input and coefficient fed directly into the device and fil-

data are both 12 bits and in two’s com- tered without separating the data into

plement format. The output is also in individual data streams.

two’s complement format and may be

able to 24-bit)

ꢀ 32-Tap FIR Filter, Cascadable for

More Filter Taps

ꢀ Over 49 K-bits of on-board Memory

ꢀ LF Interface^TMAllows All 256 Coef-

ficient Sets to be Updated Within

Vertical Blanking

ꢀ Various Operating Modes: Dual

Filter, Single Filter, Double Wide

Data or Coefficient, Matrix Multi-

plication, and Accumulator Access.

ꢀ Selectable 16-bit Data Output with

User-Defined Rounding and Limit-

ing

The LF3320 can handle a maximum of

rounded to 16 bits.

sixteen data sets interleaved together.

The LF3320 is designed to take advan- The I/D Registers and on-chip accu-

tage of symmetric coefficient sets.

When symmetric coefficient sets are

used, the device can be configured as

a single 32-tap FIR filter or as two sep-

arate 16-tap FIR filters.

mulators facilitate using decimation

to increase the number of filter taps.

Decimation of up to 16:1 is supported.

The LF3320 contains enough on-board

memory to store 256 coefficient sets.

Two separate LF Interfaces^TMallow

all 256 coefficient sets to be updated

within vertical blanking.

When asymmetric coefficient sets are

used, the device can be configured

as a single 16-tap FIR filter or as

two separate 8-tap FIR filters. Mul-

tiple LF3320s can be cascaded to create

larger filters.

ꢀ Supports Interleaved Data Streams

ꢀ Supports Decimation up to 16:1 for

Increasing Number of Filter Taps

ꢀ 3.3 Volt Supply

ꢀ 144 Lead PQFP

NOTE: loading registers via the LF

interface must not exceed 90MHz. The

PAUSE pin must be used to throttle

back the LF interface at clock speeds

above 90MHz.

LF3320 BLOCK DIAGRAM

ROUT11-0

RIN11-0

INTERLEAVE / DECIMATION

REGISTERS

DIN11-0

COUT11-0

CAA7-0

CAB7-0

CENA

CFA11-0

PAUSEA

LDA

CENB

256

CFB11-0

PAUSEB

LDB

COEFFICIENT

SET

COEFFICIENT

SET

16-TAP

FILTER A

FILTER B

STORAGE

ROUND

SELECT

LIMIT

CIRCUITRY

CLK

OED

DOUT15-0

Video Imaging Products

6/22/2007–LDS.3320-R

2-1

12 3 4 5 6 7...24

中文翻译

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与LF3320QC15G相关器件

型号	品牌	获取价格	描述	数据表
LF3320QC18	ETC	获取价格	Digital Filter
LF3320QC25	ETC	获取价格	Digital Filter
LF3320QC9	LOGIC	获取价格	Digital Filter, 12-Bit, CMOS, PQFP144, PLASTIC, QFP-144
LF3321	LOGIC	获取价格	Horizontal Digital Image Filter Improved Performance
LF3321Q5	LOGIC	获取价格	Digital Filter, PQFP144
LF3321QC9	LOGIC	获取价格	Digital Filter, 12-Bit, CMOS, PQFP144, PLASTIC, QFP-144
LF3324BGC	LOGIC	获取价格	Memory Circuit, 1MX24, CMOS, PBGA172, LBGA-172
LF3330	LOGIC	获取价格	Vertical Digital Image Filter
LF3330FMB12	ETC	获取价格	Digital Filter
LF3330FMB15	ETC	获取价格	Digital Filter

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