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LF2242QC25 PDF预览

LF2242QC25

更新时间： 2024-11-21 22:12:31
品牌 Logo 应用领域
逻辑 - LOGIC /
页数 文件大小 规格书
8页 138K
描述
12/16-bit Half-Band Interpolating/ Decimating Digital Filter

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LF2242QC25 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Contact Manufacturer零件包装代码：QFP
包装说明：QFP, QFP44,.5SQ,32针数：44
Reach Compliance Code：compliantECCN代码：3A991.A.2
HTS代码：8542.39.00.01风险等级：5.11
其他特性：2'S COMPLEMENT/INVERTED OFFSET BINARY OUTPUT; ICC SPECIFIED @ 20MHZ边界扫描：NO
最大时钟频率：40 MHz外部数据总线宽度：12
JESD-30 代码：S-PQFP-G44JESD-609代码：e0
长度：10 mm低功率模式：NO
湿度敏感等级：3端子数量：44
最高工作温度：70 °C最低工作温度：
输出数据总线宽度：16封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装等效代码：QFP44,.5SQ,32
封装形状：SQUARE封装形式：FLATPACK
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified座面最大高度：2.45 mm
子类别：DSP Peripherals最大压摆率：140 mA
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.8 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：10 mm
uPs/uCs/外围集成电路类型：DSP PERIPHERAL, DIGITAL FILTERBase Number Matches：1

LF2242QC25 数据手册

 浏览型号LF2242QC25的Datasheet PDF文件第2页浏览型号LF2242QC25的Datasheet PDF文件第3页浏览型号LF2242QC25的Datasheet PDF文件第4页浏览型号LF2242QC25的Datasheet PDF文件第5页浏览型号LF2242QC25的Datasheet PDF文件第6页浏览型号LF2242QC25的Datasheet PDF文件第7页 
LF2242  
12/16-bit Half-Band Interpolating/  
DEVICES INCORPORATED  
Decimating Digital Filter  
FEATURES  
DESCRIPTION  
The LF2242 is a linear-phase, half-  
band (low pass) interpolating/  
decimating digital filter that, unlike  
intricate analog filters, requires no  
tuning. The LF2242 can also signifi-  
cantly reduce the complexity of  
traditional analog anti-aliasing pre-  
filters without compromising the  
signal bandwidth or attenuation. This  
can be achieved by using the LF2242  
as a decimating post-filter with an  
A/D converter and by sampling the  
signal at twice the rate needed.  
Likewise, by using the LF2242 as an  
interpolating pre-filter with a D/A  
converter, the corresponding analog  
reconstruction post-filter circuitry can  
be simplified.  
sample rate. Once data is clocked in,  
the 55-value output response begins  
after 7 clock cycles and ends after 61  
clock cycles. The pipeline latency  
from the input of an impulse response  
to its corresponding output peak is 34  
clock cycles.  
❑ 40 MHz Clock Rate  
❑ Passband (0 to 0.22fS)  
Ripple: ±0.02 dB  
❑ Stopband (0.28fS to 0.5fS)  
Rejection: 59.4 dB  
❑ User-Selectable 2:1 Decimation or  
1:2 Interpolation  
The output data may be in either  
two’s complement format or inverted  
offset binary format. To avoid  
truncation errors, the output data is  
always internally rounded before it is  
latched into the output register.  
Rounding is user-selectable, and the  
output data can be rounded from 16  
bit values down to 8 bit values.  
❑ 12-bit Two’s Complement Input  
and 16-bit Output with  
User-Selectable Rounding, 8- to  
16-Bits  
❑ User-Selectable Two’s Complement  
or Inverted Offset Binary Output  
Formats  
❑ Three-State Outputs  
❑ Replaces TRW/ Raytheon/  
Fairchild TMC2242  
DC gain of the LF2242 is 1.0015  
(0.0126 dB) in pass-through and  
decimate modes and 0.5007 (–3.004  
dB) in interpolate mode. Passband  
ripple does not exceed ±0.02 dB from  
0 to 0.22fS with stopband attenuation  
greater than 59.4 dB from 0.28fS to  
0.5fS (Nyquist frequency). The  
❑ Package Styles Available:  
• 44-pin PLCC, J-Lead  
• 44-pin PQFP  
The coefficients of the LF2242 are  
fixed, and the only user programming  
required is the selection of the mode  
(interpolate, decimate, or pass-  
through) and rounding. The asyn-  
chronous three-state output enable  
control simplifies interfacing to a bus.  
response of the filter is –6 dB at 0.25fS.  
Data can be input into the LF2242 at a Full compliance with CCIR Recom-  
rate of up to 40 million samples per mendation 601 (–12 dB at 0.25fS) can  
second. Within the 40 MHz I/O limit, be achieved by cascading two devices  
the output sample rate can be one-  
half, equal to, or two times the input  
serially.  
LF2242 BLOCK DIAGRAM  
TCO RND2–0  
3
3
55-TAP  
FIR  
FILTER  
ROUND  
AND LIMIT  
CIRCUIT  
12  
12  
16  
16  
INTERPOLATION  
CIRCUIT  
DECIMATION  
CIRCUIT  
SI11–0  
SO15–0  
3
3
OE  
CLK  
TO ALL REGISTERS  
INT DEC SYNC  
Video Imaging Products  
08/16/2000–LDS.2242-K  
1
12345678

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