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LF2247JC15 PDF预览

LF2247JC15

更新时间: 2024-11-21 23:46:07
品牌 Logo 应用领域
逻辑 - LOGIC 外围集成电路输入元件LTE时钟
页数 文件大小 规格书
10页 261K
描述
Digital Filter

LF2247JC15 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Contact Manufacturer零件包装代码:LCC
包装说明:QCCJ, LDCC84,1.2SQ针数:84
Reach Compliance Code:compliantECCN代码:3A001.A.3
HTS代码:8542.39.00.01风险等级:5.78
Is Samacsys:N其他特性:4 X 10 BIT DATA INPUT; 25 BIT RESULT ACCUMULATOR
边界扫描:NO最大时钟频率:66.66 MHz
外部数据总线宽度:10JESD-30 代码:S-PQCC-J84
JESD-609代码:e0长度:29.3116 mm
低功率模式:NO湿度敏感等级:3
端子数量:84最高工作温度:70 °C
最低工作温度:输出数据总线宽度:16
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC84,1.2SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
座面最大高度:5.08 mm子类别:DSP Peripherals
最大压摆率:100 mA最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:29.3116 mmuPs/uCs/外围集成电路类型:DSP PERIPHERAL, DIGITAL FILTER
Base Number Matches:1

LF2247JC15 数据手册

 浏览型号LF2247JC15的Datasheet PDF文件第2页浏览型号LF2247JC15的Datasheet PDF文件第3页浏览型号LF2247JC15的Datasheet PDF文件第4页浏览型号LF2247JC15的Datasheet PDF文件第5页浏览型号LF2247JC15的Datasheet PDF文件第6页浏览型号LF2247JC15的Datasheet PDF文件第7页 
LF2247  
Image Filter with Coefficient RAM  
DEVICES INCORPORATED  
FEATURES  
DESCRIPTION  
The LF2247 consists of an array of four an asynchronous three-state output  
66 MHz Data Input and Compu-  
1
2
tation Rate  
11 x 10-bit registered multipliers  
followed by a summer and a 25-bit  
accumulator. The LF2247 provides a  
enable control to simplify the design  
of complex systems. The pipeline  
latency for all inputs is five clock  
Four 11 x 10-bit Multipliers with  
Individual Data and Coefficient  
Inputs and a 25-bit Accumulator  
coefficient register file containing four cycles.  
32 x 11-bit registers which are capable  
Four 32 x 11-bit Serially Loadable  
A 25-bit accumulator path allows  
cumulative word growth which may  
be internally rounded to 16 bits.  
Output data is updated every clock  
cycle and may be held under user  
control. The data inputs/outputs and  
control inputs are registered on the  
rising edge of CLK. The Serial Data In  
signal, SDIN, is registered on the  
of storing 32 different sets of filter  
coefficients for the multiplier array.  
All multiplier data inputs are user  
accessible and can be updated every  
clock cycle with either fractional or  
integer two’s complement data. The  
pipelined architecture has fully  
Coefficient Registers  
3
Fractional or Integer Two’s  
Complement Operands  
Package Styles Available:  
• 84-pinPLCC, J-Lead  
4
• 100-pin PQFP  
registered input and output ports and  
5
LF2247 BLOCK DIAGRAM  
ENBA  
6
COEFFICIENT REGISTER FILE  
5
A4-0  
7
SDIN  
SEN  
Coefficient  
Register 1  
(32 x 11-bit)  
Coefficient  
Register 2  
(32 x 11-bit)  
Coefficient  
Register 3  
(32 x 11-bit)  
Coefficient  
Register 4  
(32 x 11-bit)  
SEN  
SEN  
SEN  
SCLK  
SCLK  
SCLK  
SCLK  
8
D19-0  
10  
ENB  
1
D29-0  
10  
ENB  
2
D39-0  
10  
ENB  
3
D49-0  
10  
ENB4  
11  
11  
11  
11  
9
10  
11  
22  
22  
ACC  
25  
OCEN  
MS  
LS  
FSEL  
OEN  
CLK  
16  
TO ALL REGISTERS  
(EXCEPT COEFFICIENT REGISTERS)  
S
15-0  
Video Imaging Products  
08/16/2000–LDS.2247-H  
1

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