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LF2249QC25 PDF预览

LF2249QC25

更新时间: 2024-11-21 22:15:39
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逻辑 - LOGIC /
页数 文件大小 规格书
8页 72K
描述
12 x 12-bit Digital Mixer

LF2249QC25 数据手册

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LF2249  
12 x 12-bit Digital Mixer  
DEVICES INCORPORATED  
FEATURES  
DESCRIPTION  
user control for subtraction of prod-  
ucts. The sum of the products can  
also be internally rounded to 16 bits  
during the accumulation process.  
The LF2249 is a high-speed digital  
mixer comprised of two 12-bit  
40 MHz Data and Computation Rate  
1
2
Two 12 x 12-bit Multipliers with  
multipliers and a 24-bit accumulator.  
All multiplier inputs are user acces-  
sible, and each can be updated on  
every clock cycle. The LF2249 utilizes  
a pipelined architecture with fully  
registered inputs and outputs and an  
asynchronous three-state output  
enable control for optimum flexibility.  
Individual Data Inputs  
Separate 16-bit Input Port for  
A separate 16-bit input port con-  
nected to the accumulator is included  
to allow cascading of multiple  
LF2249s. Access to all 24 bits of the  
accumulator is gained by switching  
between upper or lower 16-bit words.  
The accumulated output data is  
updated on every clock cycle.  
Cascading Devices  
Independent, User-Selectable 1–16  
Clock Pipeline Delay for Each Data  
Input  
3
User-Selectable Rounding of Products  
Fully Registered, Pipelined  
Independent input register clock  
enables allow the user to hold the  
data inputs over multiple clock cycles.  
Each multiplier input also includes a  
user-selectable 1-16 clock pipeline  
delay. The output of each multiplier  
can be independently negated under  
4
Architecture  
Three-State Outputs  
Fully TTL Compatible  
All inputs and outputs of the LF2249  
are registered on the rising edge of  
clock, except for OE. Internal pipeline  
registers for all data and control  
inputs are provided to maintain  
5
Replaces TRW/ Raytheon/ Fairchild  
TMC2249  
120-pin PQFP  
6
LF2249 BLOCK DIAGRAM  
7
ADEL3-0  
A11-0  
ENA  
BDEL3-0  
B11-0  
ENB  
CDEL3-0  
C11-0  
ENC  
DDEL3-0  
D11-0  
END  
8
1–16  
1–16  
1–16  
1–16  
9
CLK  
10  
11  
4
4
4
4
NEG  
1
NEG  
2
RND  
FT  
ACC  
2's COMP  
2's COMP  
16  
16  
24  
CAS15-0  
3
CASEN  
SWAP  
MS  
16  
16  
LS  
1
0
0
1
2 : 1  
2 : 1  
OE  
16  
S
NOTE: NUMBERS IN REGISTERS INDICATED  
NUMBER OF PIPELINE DELAYS.  
15-0  
Video Imaging Products  
08/16/2000–LDS.2249-J  
1

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