LF2247
DEVICES INCORPORATED
Image Filter with Coefficient RAM
LF2247
Image Filter with Coefficient RAM
DEVICES INCORPORATED
FEATURES
DESCRIPTION
The LF2247 consists of an array of four an asynchronous three-state output
❑ 66 MHz Data Input and Compu-
1
2
tation Rate
11 x 10-bit registered multipliers
followed by a summer and a 25-bit
accumulator. The LF2247 provides a
enable control to simplify the design
of complex systems. The pipeline
latency for all inputs is five clock
❑ Four 11 x 10-bit Multipliers with
Individual Data and Coefficient
Inputs and a 25-bit Accumulator
coefficient register file containing four cycles.
32 x 11-bit registers which are capable
❑ Four 32 x 11-bit Serially Loadable
A 25-bit accumulator path allows
cumulative word growth which may
be internally rounded to 16 bits.
Output data is updated every clock
cycle and may be held under user
control. The data inputs/outputs and
control inputs are registered on the
rising edge of CLK. The Serial Data In
signal, SDIN, is registered on the
of storing 32 different sets of filter
coefficients for the multiplier array.
All multiplier data inputs are user
accessible and can be updated every
clock cycle with either fractional or
integer two’s complement data. The
pipelined architecture has fully
Coefficient Registers
3
❑ Fractional or Integer Two’s
Complement Operands
❑ Package Styles Available:
• 84-pinPLCC, J-Lead
4
• 100-pin PQFP
registered input and output ports and
5
LF2247 BLOCK DIAGRAM
ENBA
6
COEFFICIENT REGISTER FILE
5
A4-0
7
SDIN
SEN
Coefficient
Register 1
(32 x 11-bit)
Coefficient
Register 2
(32 x 11-bit)
Coefficient
Register 3
(32 x 11-bit)
Coefficient
Register 4
(32 x 11-bit)
SEN
SEN
SEN
SCLK
SCLK
SCLK
SCLK
8
D19-0
10
ENB
1
D29-0
10
ENB
2
D39-0
10
ENB
3
D49-0
10
ENB4
11
11
11
11
9
10
11
22
22
ACC
25
OCEN
MS
LS
FSEL
OEN
CLK
16
TO ALL REGISTERS
(EXCEPT COEFFICIENT REGISTERS)
S
15-0
Video Imaging Products
08/16/2000–LDS.2247-H
1