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LA4064V-75TN128E

更新时间： 2024-11-09 03:50:15
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莱迪思 - LATTICE 可编程逻辑器件
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42页 240K
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3.3V/1.8V In-System Programmable SuperFAST High Density PLDs

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 浏览型号LA4064V-75TN128E的Datasheet PDF文件第2页浏览型号LA4064V-75TN128E的Datasheet PDF文件第3页浏览型号LA4064V-75TN128E的Datasheet PDF文件第4页浏览型号LA4064V-75TN128E的Datasheet PDF文件第5页浏览型号LA4064V-75TN128E的Datasheet PDF文件第6页浏览型号LA4064V-75TN128E的Datasheet PDF文件第7页 
LA-ispMACH 4000V/Z  
Automotive Family  
3.3V/1.8V In-System Programmable  
TM  
SuperFAST High Density PLDs  
July 2008  
Data Sheet DS1017  
• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI  
interfaces  
• Hot-socketing  
Features  
■ High Performance  
• f  
= 168MHz maximum operating frequency  
MAX  
• Open-drain capability  
• t = 7.5ns propagation delay  
PD  
• Input pull-up, pull-down or bus-keeper  
• Programmable output slew rate  
• 3.3V PCI compatible  
• IEEE 1149.1 boundary scan testable  
• 3.3V/2.5V/1.8V In-System Programmable  
(ISP™) using IEEE 1532 compliant interface  
• I/O pins with fast setup path  
• Lead-free (RoHS) package  
• Up to four global clock pins with programmable  
clock polarity control  
• Up to 80 PTs per output  
■ Ease of Design  
• Enhanced macrocells with individual clock,  
reset, preset and clock enable controls  
• Up to four global OE controls  
• Individual local OE control per I/O pin  
• Excellent First-Time-FitTM and refit  
• Fast path, SpeedLockingTM Path, and wide-PT  
path  
Introduction  
The high performance LA-ispMACH 4000V/Z automo-  
tive family from Lattice offers a SuperFAST CPLD solu-  
tion that is tested and qualified to the AEC-Q100  
• Wide input gating (36 input logic blocks) for fast  
counters, state machines and address decoders standard. The family is a blend of Lattice’s two most  
popular architectures: the ispLSI® 2000 and ispMACH  
■ Zero Power (LA-ispMACH 4000Z)  
4A. Retaining the best of both families, the LA-ispMACH  
• Typical static current 10µA (4032Z)  
4000V/Z architecture focuses on significant innovations  
• 1.8V core low dynamic power  
to combine the highest performance with low power in a  
• LA-ispMACH 4000Z operational down to 1.6V  
flexible CPLD family.  
■ AEC-Q100 Tested and Qualified  
The LA-ispMACH 4000V/Z automotive family combines  
high speed and low power with the flexibility needed for  
ease of design. With its robust Global Routing Pool and  
Output Routing Pool, this family delivers excellent First-  
Time-Fit, timing predictability, routing, pin-out retention  
and density migration.  
• Automotive: -40 to 125°C ambient (T )  
A
■ Easy System Integration  
• Superior solution for power sensitive consumer  
applications  
• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O  
• Operation with 3.3V (4000V) or 1.8V (4000Z)  
supplies  
Table 1. LA-ispMACH 4000V Automotive Family Selection Guide  
LA-ispMACH 4032V  
LA-ispMACH 4064V  
LA-ispMACH 4128V  
Macrocells  
32  
30+2/32+4  
7.5  
64  
128  
I/O + Dedicated Inputs  
30+2/32+4/64+10  
64+10/92+4/96+4  
t
(ns)  
7.5  
4.5  
7.5  
4.5  
PD  
t (ns)  
4.5  
S
t
f
(ns)  
4.5  
4.5  
4.5  
CO  
(MHz)  
168  
168  
3.3V  
168  
3.3V  
MAX  
Supply Voltage (V)  
Pins/Package  
3.3V  
44-pin Lead-Free TQFP  
48-pin Lead-Free TQFP  
44-pin Lead-Free TQFP  
48-pin Lead-Free TQFP  
100-pin Lead-Free TQFP  
100-pin Lead-Free TQFP  
128-pin Lead-Free TQFP  
144-pin Lead-Free TQFP  
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand  
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.  
www.latticesemi.com  
1
DS1017_02.3  
1234567...42

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