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L8600 PDF预览

L8600

更新时间: 2024-10-19 21:12:15
品牌 Logo 应用领域
友顺 - UTC 光电二极管
页数 文件大小 规格书
8页 131K
描述
Analog Circuit, PDSO20

L8600 技术参数

生命周期:ActiveReach Compliance Code:compliant
风险等级:5.6JESD-30 代码:R-PDSO-G20
端子数量:20最高工作温度:70 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
电源:5 V认证状态:Not Qualified
子类别:Other Analog ICs标称供电电压 (Vsup):5 V
表面贴装:YES温度等级:OTHER
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUALBase Number Matches:1

L8600 数据手册

 浏览型号L8600的Datasheet PDF文件第2页浏览型号L8600的Datasheet PDF文件第3页浏览型号L8600的Datasheet PDF文件第4页浏览型号L8600的Datasheet PDF文件第5页浏览型号L8600的Datasheet PDF文件第6页浏览型号L8600的Datasheet PDF文件第7页 
UTCL8600  
LINEAR INTEGRATED CIRCUIT  
FET BIAS CONTROLLER  
DESCRIPTION  
The UTC L8600 is designed to meet the bias requirements  
of GaAs and HEMT FETs commonly used in satellite receiver  
LNBs, PMR, cellular telephones etc. with a minimum of  
external components.  
With the addition of two capacitors and resistors the  
devices provide drain voltage and current control for a  
number of external grounded source FETs, generating the  
regulated negative rail required for FET gate biasing whilst  
operating from a single supply. This negative bias, at -3 volts,  
can also be used to supply other external circuits.  
The UTC L8600 contains six bias stages respectively. In  
setting drain current the UTC L8600 two resistors splite  
control between two and four FETs. This allows the operating  
current of input FETs to be adjusted to minimize noise, whilst  
the following FET stages can separately be adjusted for  
maximum gain. The UTC L8600 gives 2.2 volts drain to be  
set for FETs.  
SSOP-20(150mil)  
FEATURES  
* Provides bias for GaAs and HEMT FETs  
* Drives up to six FETs  
These devices are unconditionally stable over the full  
working temperature with the FETs in place, subject to the  
inclusion of the recommended gate and drain capacitors.  
These ensure RF stability and minimal injected noise.  
It is possible to use less than the devices full complement  
of FET bias controls, unused drain and gate connections can  
be left open circuit without affecting operation of the  
remaining bias circuits.  
In order to protect the external FETs the circuits have been  
designed to ensure that, under any conditions including  
power up/down transients, the gate drive from the bias  
circuits cannot exceed the range -3.5V to 0.7V.Furthermore if  
the negative rail experiences a fault conditions, such as  
overload or short circuit, the drain supply to the FETs will shut  
down avoiding excessive current flow.  
* Dynamic FET protection  
* Drain current set by external resistor  
* Regulated negative rail generator requires only  
2 external capacitors  
* Choice in drain voltage  
* Wide supply voltage range  
APPLICATIONS  
* Satellite receiver LNBs  
* Private mobile radio(PMR)  
* Cellular telephones  
1
UTC UNISONIC TECHNOLOGIES CO., LTD.  
QW-R123-004,A  

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