Datasheet > L8400

L8400

更新时间： 2024-11-21 19:54:47

品牌	Logo	应用领域
友顺 - UTC		光电二极管
页数	文件大小	规格书
7页	111K
描述
Analog Circuit, PDSO16

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L8400 技术参数

生命周期：	Active	Reach Compliance Code：	compliant
风险等级：	5.6	JESD-30 代码：	R-PDSO-G16
端子数量：	16	最高工作温度：	70 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装等效代码：	SSOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, SHRINK PITCH
电源：	5 V	认证状态：	Not Qualified
子类别：	Other Analog ICs	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	温度等级：	OTHER
端子形式：	GULL WING	端子节距：	0.635 mm
端子位置：	DUAL	Base Number Matches：	1

L8400 数据手册

UTCL8400

LINEAR INTEGRATED CIRCUIT

FET BIAS CONTROLLER

DESCRIPTION

The UTC L8400 is designed to meet the bias requirements

of GaAs and HEMT FETs commonly used in satellite receiver

LNBs, PMR, cellular telephones etc. with a minimum of

external components.

With the addition of two capacitors and resistors the

devices provide drain voltage and current control for a

number of external grounded source FETs, generating the

regulated negative rail required for FET gate biasing whilst

operating from a single supply. This negative bias, at –3

volts, can also be used to supply other external circuits.

The UTC L8400 contains four bias stages respectively. In

setting drain current the L8400 two resistors allows individual

FET pair control to different levels. This allows the operating

current of input FETs to be adjusted to minimize noise, whilst

the following FET stages can separately be adjusted for

maximum gain. The UTC L8400 gives 2.2 volts drain whilst .

These devices are unconditionally stable over the full

working temperature with the FETs in place, subject to the

inclusion of the recommended gate and drain capacitors.

These ensure RF stability and minimal injected noise.

It is possible to use less than the devices full complement

of FET bias controls, unused drain and gate connections can

be left open circuit without affecting operation of the

remaining bias circuits.

SSOP-16(150mil)

FEATURES

* Provides bias for GaAs and HEMT FETs

* Drives up to four or six FETs

* Dynamic FET protection

* Drain current set by external resistor

* Regulated negative rail generator requires only

2 external capacitors

* Choice in drain voltage

* Wide supply voltage range

In order to protect the external FETs the circuits have been

designed to ensure that, under any conditions including

power up/down transients, the gate drive from the bias

circuits cannot exceed the range –3.5V to 0.7V.Furthermore if

the negative rail experiences a fault conditions, such as

overload or short circuit, the drain supply to the FETs will shut

down avoiding excessive current flow.

APPLICATIONS

* Satellite receiver LNBs

* Private mobile radio(PMR)

* Cellular telephones

UTC UNISONIC TECHNOLOGIES CO., LTD.

QW-R123-001,A

12 3 4 5 6 7

中文翻译

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与L8400相关器件

型号	品牌	获取价格	描述	数据表
L8400G-R16-R	UTC	获取价格	Analog Circuit, PDSO16
L8400G-R16-T	UTC	获取价格	Analog Circuit, PDSO16
L8400L-R16-T	UTC	获取价格	Analog Circuit, PDSO16
L8401	UTC	获取价格	FET BIAS CONTROLLER
L8401_15	UTC	获取价格	FET BIAS CONTROLLER
L8401_17	UTC	获取价格	FET BIAS CONTROLLER
L8401G-R16-R	UTC	获取价格	FET BIAS CONTROLLER
L8401G-R16-T	UTC	获取价格	FET BIAS CONTROLLER
L840-1JX1-43	BEL	获取价格	Telecom and Datacom Connector
L8401L-R16-R	UTC	获取价格	FET BIAS CONTROLLER

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