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L7C108 PDF预览

L7C108

更新时间： 2024-11-11 11:38:51
品牌 Logo 应用领域
逻辑 - LOGIC /
页数 文件大小 规格书
15页 666K
描述
128K x 8 Static RAM

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中文翻译

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L7C108 数据手册

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L7C108  
PRELIMINARY INFORMATION L7C109  
128K x 8 Static RAM  
Pin Configuration  
FEATURES  
128K x 8 Static RAM with Chip  
32-pin Ceramic DIP  
32-pin Ceramic SOJ  
Select Powerdown, Output Enable  
and Single or Dual Chip Selects  
32-pin Quad CLCC  
32-pin Ceramic LCC  
High Speed — to 15 ns maximum  
Operational Power, -L Version  
Active: 140 mA at 15 ns  
Standby: 1 mA max  
1
2
3
4
5
6
7
8
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
NC  
V
A
CE  
CC  
15  
1
2
3
4
5
6
7
8
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
NC  
V
A
CE  
WE  
CC  
15  
A
A
A
16  
14  
12  
A16  
A14  
A12  
4
3
2
1
32 31 30  
29  
2
2
WE  
5
6
7
8
9
A7  
A6  
A5  
A4  
A3  
WE  
A13  
A8  
A
A
A
A
A
A
A
A
7
6
5
4
3
2
1
0
1
2
3
A
A
A
A
OE  
A10  
CE  
DQ  
DQ  
DQ  
DQ  
DQ  
13  
8
A
A
A
A
A
A
A
A
7
6
5
4
3
2
1
0
1
2
3
A
A
A
A
13  
Data Retention at 2 V for Battery  
Backup Operation  
28  
27  
26  
25  
24  
23  
22  
21  
8
9
9
A9  
11  
Top  
View  
11  
Screened to MIL-STD-883, Class B  
or to SMD 5962-89598  
A11  
OE  
A10  
CE1  
DQ8  
9
9
OE  
A10  
A2 10  
A1 11  
A0 12  
10  
11  
12  
13  
14  
15  
16  
10  
11  
12  
13  
14  
15  
16  
Package Styles Available:  
CE  
DQ  
DQ  
DQ  
DQ  
DQ  
8
7
6
5
4
8
7
6
5
4
ꢀ 32-pin Ceramic 400mil DIPꢁꢂD12ꢃ  
ꢀ 32-pin Ceramic LCCꢁꢂK11ꢃ  
ꢀ 32-pin Ceramic SOꢄꢁꢂꢅ1ꢃ  
DQ1 13  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
14 15 16 17 18 19 20  
VSS  
VSS  
ꢀ 32-pin ꢆuad Ceramic LCCꢁꢂKA1ꢃ  
OVERVIEW  
The L7C108 and L7C109 are high-perfor-  
mance, low-power CMOS static RAMs.  
The storage circuitry is organized as  
131,072 words by 8 bits per word. The  
8 Data In and Data Out signals share I/O  
pins. The L7C108 has a single active-  
low Chip Enable. The L7C109 has two  
Chip Enables ꢁone active-lowꢃ. These  
devices are available in three speeds  
with maximum access times from 15 ns  
to 45 ns.  
Chip Enables and a three-state I/O bus  
with a separate Output Enable control  
simplify the connection of several chips  
for increased storage capacity.  
may be used to terminate the write oper-  
ation. Data In and Data Out signals have  
the same polarity.  
Latchup and static discharge protection  
are provided on-chip. The L7C108 and  
L7C109 can withstand an injection cur-  
rent of up to 200 mA on any pin without  
damage.  
Memory locations are specified on  
address pins A0 through A16. For the  
L7C108, reading from a designated  
location is accomplished by present-  
ing an address and driving CE1 and OE  
LOW while WE remains HIGH. For the  
L7C109, CE1 and OE must be LOW  
while CE2 and WE are HIGH.The data in  
the addressed memory location will then  
appear on the Data Out pins within one  
access time. The output pins stay in a  
high-impedance state when CE1 or OE is  
HIGH, or CE2 ꢁL7C109ꢃ or WE is LOW.  
Writing to an addressed location is  
accomplished when the active-low CE1  
and WE inputs are both LOW, and CE2  
ꢁL7C109ꢃ is HIGH. Any of these signals  
Inputs and outputs are TTL compatible.  
Operation is from a single +5 V power  
supply. Power consumption is 140 mA  
ꢁ-L Versionꢃ at 15 ns. Data may be  
retained in inactive storage with a supply  
voltage as low as 2 V.  
The L7C108 and L7C109 provide asyn-  
chronous ꢁunclockedꢃ operation with  
matching access and cycle times. The  
1M Static RAMs  
LOGIC Devices Incorporated  
www.logicdevices.com  
1
Aug 11, 2010 LDS-L7C108/9-F  
1234567...15

中文翻译

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与L7C108相关器件

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L7C108CC15 ETC

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L7C108CC15L LOGIC

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 		Standard SRAM, 128KX8, 15ns, CMOS, CDIP32, 0.400 INCH, CERAMIC, DIP-32
L7C108CC17 ETC

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L7C108CC17L ETC

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 		x8 SRAM
L7C108CC20 LOGIC

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 		Standard SRAM, 128KX8, 20ns, CMOS, CDIP32, 0.400 INCH, CERAMIC, DIP-32
L7C108CC20L LOGIC

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 		Standard SRAM, 128KX8, 20ns, CMOS, CDIP32, 0.400 INCH, CERAMIC, DIP-32
L7C108CC25 LOGIC

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 		Standard SRAM, 128KX8, 25ns, CMOS, CDIP32, 0.400 INCH, CERAMIC, DIP-32
L7C108CC25L ETC

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 		x8 SRAM
L7C108CM17 ETC

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 		x8 SRAM
L7C108CM17L LOGIC

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 		Standard SRAM, 128KX8, 17ns, CMOS, CDIP32, 0.400 INCH, CERAMIC, DIP-32

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