5秒后页面跳转
捷配首页

Datasheet > L7C108DC15L
L7C108DC15L PDF预览

L7C108DC15L

更新时间： 2024-09-30 19:55:07
品牌 Logo 应用领域
逻辑 - LOGIC 静态存储器内存集成电路
页数 文件大小 规格书
9页 166K
描述
Standard SRAM, 128KX8, 15ns, CMOS, CDIP32, 0.400 INCH, HERMETIC SEALED, SIDE BRAZED, DIP-32

阅读下载

中文翻译

获取价格

L7C108DC15L 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP, DIP32,.4
针数：32Reach Compliance Code：unknown
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.88最长访问时间：15 ns
其他特性：AUTOMATIC POWER-DOWNI/O 类型：COMMON
JESD-30 代码：R-CDIP-T32JESD-609代码：e0
长度：40.64 mm内存密度：1048576 bit
内存集成电路类型：STANDARD SRAM内存宽度：8
湿度敏感等级：3功能数量：1
端口数量：1端子数量：32
字数：131072 words字数代码：128000
工作模式：ASYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：128KX8
输出特性：3-STATE可输出：YES
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：DIP
封装等效代码：DIP32,.4封装形状：RECTANGULAR
封装形式：IN-LINE并行/串行：PARALLEL
峰值回流温度（摄氏度）：225电源：5 V
认证状态：Not Qualified座面最大高度：4.953 mm
最大待机电流：0.0001 A最小待机电流：2 V
子类别：SRAMs最大压摆率：0.215 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：10.16 mm
Base Number Matches：1

L7C108DC15L 数据手册

 浏览型号L7C108DC15L的Datasheet PDF文件第2页浏览型号L7C108DC15L的Datasheet PDF文件第3页浏览型号L7C108DC15L的Datasheet PDF文件第4页浏览型号L7C108DC15L的Datasheet PDF文件第5页浏览型号L7C108DC15L的Datasheet PDF文件第6页浏览型号L7C108DC15L的Datasheet PDF文件第7页 
L7C108/109  
128K x 8 Static RAM (Low Power)  
DEVICES INCORPORATED  
FEATURES  
DESCRIPTION  
The L7C108 and L7C109 are high-  
performance, low-power CMOS static  
RAMs. The storage circuitry is organ-  
ized as 131,072 words by 8 bits per  
word. The 8 Data In and Data Out  
signals share I/O pins. The L7C108 has  
a single active-low Chip Enable. The  
L7C109 has two Chip Enables (one  
active-low). These devices are available  
inthree speeds with maximum access  
times from 10 ns to 15 ns.  
consume only 1.5 mW (typical), at 3 V,  
allowing effective battery backup  
operation.  
q 128K x 8 Static RAM with Chip  
Select Powerdown, Output Enable  
q Auto-Powerdown™ Design  
q Advanced CMOS Technology  
q High Speed — to 10 ns maximum  
q Low Power Operation  
Active: 570 mW typical at 15 ns  
Standby: 5 mW typical  
The L7C108 and L7C109 provide  
asynchronous (unclocked) operation  
with matching access and cycle times.  
The Chip Enables and a three-state I/O  
bus with a separate Output Enable  
control simplify the connection of  
several chips for increased storage  
capacity.  
q Data Retention at 2 V for Battery  
Backup Operation  
q DSCC SMD No. 5962-89598  
Inputs and outputs are TTL compat-  
ible. Operation is from a single +5 V  
power supply. Power consumption  
is 930 mW (typical) at 10 ns. Dissipa-  
tion drops to 50 mW (typical) when  
the memory is deselected.  
q Available 100% Screened to  
Memory locations are specified on  
address pins A0 through A16. For the  
L7C108, reading from a designated  
location is accomplished by presenting  
an address and driving CE1 and OE  
LOW while WE remains HIGH. For  
the L7C109, CE1 and OE must be  
LOW while CE2 and WE are HIGH.  
The data in the addressed memory  
location will then appear on the Data  
Out pins within one access time. The  
output pins stay in a high-impedance  
state when CE1 or OE is HIGH, or CE2  
(L7C109) or WE is LOW.  
MIL-STD-883, Class B  
q Plug Compatible with Cypress  
CY7C108/109, IDT71024/71B024,  
Micron MT5C1008, Motorola  
MCM6226A/62L26A, Sony  
CXK581020  
q Package Styles Available:  
• 32-pin Sidebraze, Hermetic DIP  
• 32-pin Plastic SOJ  
Two standby modes are available.  
Proprietary Auto-Powerdown™  
circuitry reduces power consumption  
automatically during read or write  
accesses which are longer than the  
minimum access time, or when the  
memory is deselected. In addition,  
data may be retained in inactive  
storage with a supply voltage as low  
as 2 V. The L7C108 and L7C109  
• 32-pin Ceramic LCC  
• 32-pin Ceramic SOJ  
Writing to an addressed location is  
accomplished when the active-low  
CE1 and WE inputs are both LOW,  
and CE2 (L7C109) is HIGH. Any of  
these signals may be used to terminate  
the write operation. Data In and Data  
Out signals have the same polarity.  
L7C108/109 BLOCK DIAGRAM  
Latchup and static discharge protection  
are provided on-chip. The L7C108 and  
L7C109 can withstand an injection  
current of up to 200 mA on any pin  
without damage.  
512 x 256 x 8  
MEMORY  
ARRAY  
9
ROW  
ADDRESS  
CE  
1
8
COLUMN SELECT  
I/O7-0  
WE  
OE  
CONTROL  
& COLUMN SENSE  
OBSOLETE  
CE  
2
(L7C109 only)  
8
COLUMN ADDRESS  
1M Static RAMs  
03/04/99–LDS.108/9-N  
1
1234567...9

中文翻译

下载PDF

与L7C108DC15L相关器件

型号 品牌 获取价格 描述 数据表
L7C108DC17 ETC

获取价格

 		x8 SRAM
L7C108DC17L LOGIC

获取价格

 		Standard SRAM, 128KX8, 17ns, CMOS, CDIP32, 0.400 INCH, HERMETIC SEALED, SIDE BRAZED, DIP-3
L7C108DC20 ETC

获取价格

 		x8 SRAM
L7C108DC20L LOGIC

获取价格

 		Standard SRAM, 128KX8, 20ns, CMOS, CDIP32, 0.400 INCH, HERMETIC SEALED, SIDE BRAZED, DIP-3
L7C108DC25 ETC

获取价格

 		x8 SRAM
L7C108DC25L LOGIC

获取价格

 		Standard SRAM, 128KX8, 25ns, CMOS, CDIP32, 0.400 INCH, HERMETIC SEALED, SIDE BRAZED, DIP-3
L7C108DEB20 LOGIC

获取价格

 		Standard SRAM, 128KX8, 20ns, CMOS, CDIP32
L7C108DEB25 LOGIC

获取价格

 		Standard SRAM, 128KX8, 25ns, CMOS, CDIP32
L7C108DEB25L LOGIC

获取价格

 		Standard SRAM, 128KX8, 25ns, CMOS, CDIP32
L7C108DIB15 LOGIC

获取价格

 		Standard SRAM, 128KX8, 15ns, CMOS, CDIP32

与L7C108DC15L相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证